LS2160A Serdes Clocking

[kiron]

I'm using LX2160A SerDes1 with RCW SerDes Protocol 2:

Lanes E–H: SGMII
Lanes A–D: PCIe.2 x4 (Gen2 only)

From the Reference Manual, it appears all lanes use PLLS, so both SGMII and PCIe must share the same reference clock. I originally wanted to run SGMII at 125 MHz and PCIe at 100 MHz using separate fast/slow clock inputs, but since this specific protocol option puts both protocols on PLLS only, they must share one identical reference frequencyso now I plan to provide a single 100 MHz clock to the SD1 PLLS input and leave PLLF unused.

Is it possible to run Protocol 2 with a single 100 MHz PLLS reference for both SGMII and PCIe Gen1/Gen2, with no additional SerDes configuration beyond the RCW?
Are there any protocol-specific issues (jitter, SSC, etc.) when SGMII and PCIe share the same PLLS?
My SGMII link partner is a LAN9645 using its own local 125 MHz reference. Since SGMII uses CDR, is it normal for one side to be derived from 100 MHz and the other from 125 MHz, as long as both generate the correct 1.25 Gbaud line rate?
Since Protocol 2 doesn't use PLLF, can the SD1 fast reference clock input be left unconnected, or should it still be driven?

[yipingwang]

Yes. For LX2160A SerDes1 Protocol 2, the initial PLL mapping is all PLLS: lanes H–E are SGMII and lanes D–A are PCIe.2 x4. If PCIe is limited to Gen1/Gen2 using SRDS_DIV_PEX_S1 = 0b10 or 0b11, a single fixed 100 MHz reference on SD1 PLLS is valid for both SGMII 1.25 Gbaud and PCIe Gen1/Gen2. No additional SerDes PLL reconfiguration is required beyond correct RCW settings.

Do not use spread-spectrum on this shared PLLS reference, because the Reference Manual states that when SSC is used for a PCIe SerDes reference clock, the same SerDes PLL must not be used concurrently for other protocols. Use a fixed, low-jitter 100 MHz clock.

It is normal for the SGMII peer to use its own local 125 MHz reference while the LX2160A derives SGMII from 100 MHz, because each SGMII receiver uses CDR and both sides only need to generate a compliant 1.25 Gbaud serial stream.

Since PLLF is not used in this Gen1/Gen2-only configuration, SD1_PLLF_REF_CLK may be left un-driven only if the RCW disables the PLLF reference clock and powers down PLLF. If Gen3 may ever be enabled, PLLF must be provided with a valid reference clock, because Protocol 2 switches PCIe lanes to PLLF at Gen3.

[kiron]

Does SGMII support 1.25G Baudrate or 2.5G Baudrate. Does 2.5G require a different clocking other than 100Mhz.

[yipingwang]

 1.25G Baudrate

Please refer to "26.1.7 Reference Clocks for SerDes Protocols" in LX2160A Reference Manual.