I'm using LX2160A SerDes1 with RCW SerDes Protocol 2:
Lanes E–H: SGMII
Lanes A–D: PCIe.2 x4 (Gen2 only)
From the Reference Manual, it appears all lanes use PLLS, so both SGMII and PCIe must share the same reference clock. I originally wanted to run SGMII at 125 MHz and PCIe at 100 MHz using separate fast/slow clock inputs, but since this specific protocol option puts both protocols on PLLS only, they must share one identical reference frequencyso now I plan to provide a single 100 MHz clock to the SD1 PLLS input and leave PLLF unused.
Is it possible to run Protocol 2 with a single 100 MHz PLLS reference for both SGMII and PCIe Gen1/Gen2, with no additional SerDes configuration beyond the RCW?
Are there any protocol-specific issues (jitter, SSC, etc.) when SGMII and PCIe share the same PLLS?
My SGMII link partner is a LAN9645 using its own local 125 MHz reference. Since SGMII uses CDR, is it normal for one side to be derived from 100 MHz and the other from 125 MHz, as long as both generate the correct 1.25 Gbaud line rate?
Since Protocol 2 doesn't use PLLF, can the SD1 fast reference clock input be left unconnected, or should it still be driven?
