LS1046a DDR ECC Error Injection

[zwolbers-blue]

Hello,

I'm attempting to verify that the error detection software we've developed works as expected.  To that end, I'm trying to manually induce an ECC error in RAM using the LS1046a DDR Memory Controller.

Using register descriptions as a guide, I've pieced together the following procedure.  Unfortunately, no errors are detected.  Any ideas?

1. Boot into U-Boot
2. Attach a Lauterbach debugger, and break execution
3. Verify DDR_SDRAM_CFG[ECC_EN] is 1 (ECC enabled)
4. Set DDR_SDRAM_CFG_3[ECC_FIX_EN] to 1 (enable ECC fixing)
5. Verify DDR_SDRAM_CFG_3[ECC_SCRUB_INT] is 0x0 (disable ECC scrubbing)
6. Verify DATA_ERR_INJECT_HI is 0 (do not inject data errors)
7. Verify DATA_ERR_INJECT_LO is 0 (do not inject data errors)
8. Set ECC_ERR_INJECT[EEIM] to 0x01 (inject 1 bit ECC parity errors)
9. Set ECC_ERR_INJECT[EIEN] to 1 (error injection enabled)
10. Verify ERR_DISABLE is 0 (all error detection enabled)
11. Set ERR_SBE[SSBET] to 1 (scrubbed single-bit error threshold)
12. Set ERR_SBE[SBET] to 1 (single-bit error threshold)
13. Resume execution
14. In U-Boot, run `mw 0xa0000000 1` (initialize a word to 0x1; the DDR controller should automatically inject a 1 bit error to the ECC parity bits)
15. In U-Boot, run `md 0xa0000000` (read the same word back; the DDR controller should automatically detect and fix the parity error, and set a flag in ERR_DETECT)
16. Check ERR_DETECT (an error flag should be set, but never is)

Thanks for your time.

[yipingwang]

ECC function is guaranteed by hardware, no chance for malfunction. Injection test requires following sequence (this assumes DDR controller is up with D_INIT bit set and cache disabled):

1) DATA_ERR_INJECT_LO = 00000001 (the LSbit of 64-bit word is going to be inverted);

2) ERR_INJECT[EIEN]=1; enable injection 2a) read back ERR_INJECT to make sure it has been written;

3) write 0x0000000000000000 to some DDR location (actually 0x0000000000000001 will be written due to above steps);

4) repeat step 3 for a number of address locations to inject the number of single bit errors;

5) ERR_INJECT[EIEN]=0; disable injection

Reading of the location used in step 3 should result in value 0000000000000000 (LSbit is corrected). ERR_DETECT register should report  a single-bit ECC error, ERR_SBE[SBEC] counts errors.