LS1046ARDB DDR DQ Mapping

[dshekter]

I have an LS1046ARDB and I'm trying to configure the DDR controller for DDR validation tool usage. I have confirmed that out of the box the DDR validation tool runs and passes with plenty of voltage and timing margin. However, I'm very confused by the DQ mapping. The schematic and datasheets for the parts + DIMM that are installed show a 1:1 mapping, no swizzling. But, the DDQ_DQ_MAP registers both in the target initialization file and as passing in the DDR validation are very much not 1:1. The values are not 0 (default), 0x01, 0x21, or anything else that would make sense. In fact, they're not even consistently different. The values for DQ[0:3] and DQ[8:11] differ despite in the schematic them both showing up the same. I tried changing the values and got varying error messages, including if I set everything to 0.

Reading the revision history of the schematic, it looks like initially development was done with an LS1043A on an interposer. Is it possible this is an artifact of that and the schematic is incorrect?

[dshekter · Accepted solution]

I figured it out. There's a region in the SPD data for the DQ mapping that matches what was in the validation tool.