Hello,
I have a very dumb question: We are designing a new board (core speed 1.8GHz) and need to connect the SoC to an FPGA via PCIe as well as via IFC (IFC for latency reasons for certain data transfers). As I understand it with the fastest possible platform clock frequency (700MHz) the fastest possible IFC clock speed is 87.5MHz (IFC_CCR divider = 4). If I choose the max. possible IFC frequency of 100MHz the max. possible platform clock frequency would be 400MHz only (IFC_CCR divider = 2). Can this really be true?
