LS1046A: How to power down a core

[scottwelsh]

Per my system requirements I need to power down 3 of the 4 cores. Can someone point me to the documentation which discusses how to shut down the specific clocks for 3 of the 4 cores?

Thank you

[changjake]

Hi Daves,

I also need to disable cores in my custom LS1046a board.

I added bellow lines in components/firmware/rcw/ls1046a_custom/NN_FNSNPPPP_1133_8888/rcw_1600_qspiboot.rcw:

---

//-------------------------------------------------------------------------
// disable core 3 and 2 so we only use core 0 and 1...
.pbi
write 0x01EE0094, 0x0000000c
//write 0x01ee0094, 0x0000000e
.end

---

I rebuilt firmware_ls1046a_custom_qspiboot.img & flashed on my custom board.
But, nothing displayed in the console.

Is there anything to change more?

Regards,
Jake

[Daves_Garage]

Hi Jake,

My guess there's no response on the serial output is because you threw an error during the PBL portion of the boot process... The LS1046A is not very friendly if the RCW or the PBL is wrong; if the CRC doesn't match, it simply stops and sets the RESET_REQ line to reboot itself... which sends it into an endless loop if that's how your hardware is setup...

The problem with your code is the address.  The commands in the PBL strip off the most significant (1) in your address, and incorporate it into the WRITE macro you're using.

If you change your PBL line to this:

.pbi
write 0x0EE0094, 0x0000000c
.end

it probably will work for you...

Hope this helps.

-Dave

[changjake]

Hi Dave,
It works!
Thank you so much.

Regards,
Jake

[Daves_Garage]

Happy to help.  Good luck!

[Daves_Garage]

Hi Scott,  I just was looking into doing this myself when I ran across this unanswered question... I've sort of given up on this forum, as no one seems to respond for a really long time... looks like you asked your question over 5 months ago with no response.

Well, to show you what I did, here's a shot of my notes:

DISABLING CORES ON LS1046A

ref: 12.3.11 Core Disable Register (COREDISR)

• COREDISR provides a mechanism for gating clocks to any cores on the device that are not used when running an application.
• COREDISR register should only be configured in the following conditions:
  • Before system ready, COREDISR register can be programmed by the external debugger or Pre-Boot Initialization.
  • After system ready, a COREDISR register bit can be programmed for the corresponding core by the external debugger or embedded software while the core is in boot-holdoff mode.

HOW TO…

• DCFG_CCSR base address: 0x01EE0000
• COREDISR address: 0x01EE0094

Value Definition

0x000000002	Core 1 disabled
0x000000004	Core 2 disabled
0x000000008	Core 3 disabled

Values can be OR’d together to disable multiple cores.

Core 0 is always enabled…

Example:

    //-------------------------------------------------------------------------
    // disable core 3 and 2 so we only use core 0 and 1...
    //-------------------------------------------------------------------------
    write 0xEE0094, 0x0000000C

MODIFY U-BOOT TO REFLECT IDLE CORES

• Change code in ./u-boot/arch/arm/cpu/armv8/fsl-layerscape/cpu.c

for_each_cpu(i, core, cpu_numcores(), cpu_mask()) {
    if(!(i % 2)) 
        printf("\n\t");

    type = TP_ITYP_VER(fsl_qoriq_core_to_type(core));

    printf("CPU%d(%s):%-4s MHz %s ", core,
           (type == TY_ITYP_VER_A7) ? "A7 " :
              (type == TY_ITYP_VER_A53 ? "A53" :
              (type == TY_ITYP_VER_A57 ? "A57" :
              (type == TY_ITYP_VER_A72 ? "A72" : "   "))),
              strmhz(buf, sysinfo.freq_processor[core]),
              (in_be32(0x01EE0094) & (1<<core)) ? "[ IDLE ]" : "[ACTIVE]");
    }