LS1046 without DDR4 memory

[BernhardF]

Hi,

i am currently looking into a custom design centered by the LS1046a SoC. Due to some constraints we will not be able to place a DDR4 memory chip on the board. Also to my understanding DDR3 is not possible with the LS1046a.

Is it possible to define a setup which can live without the DDR4 memory?

One upside is that the application i try to develop could be small enough to fit into the 2MB L2 cache (Application and Data). Has anyone tried this before or is there maybe an absolute show-stopper i am not seeing?

regards

Bernhard

[ufedor]

LS1046A has Cortex-A72 ARMv8 processor having integrated L2 cache controller which does not allow to configure L2 cache as SRAM.

Also in the A72 TRM, "7.1 About the L2 memory system" it is explicitly noted that L2 cache locking is not supported:

"The Cortex-A72 processor does not support TLB or cache lockdown."

So LS1046A L2 cache cannot be used as SRAM.

[BernhardF]

Hi Ufedor,

thanks for the clarification about the L2-Cache. Would it be possible to perform Execute-In-Place from a NOR-Flash attached to SPI?

Considering only 1 Core used and the application is small enough so that the penalty concerning instruction fetch and write back is negligible. To my understanding this could work. Its clear to me that iff this approach works the resulting performance will be much lower compared to a DDR memory attached. Also wear-level management could be a problem when we would constantly write data to the NOR-flash.

regards Bernhard

[ufedor · Accepted solution]

> Would it be possible to perform Execute-In-Place from a NOR-Flash attached to SPI?

Yes.