LS1046 RESET_REQ and RSTRQSR

[SimonRo]

We are seeing RESET_REQ_B asserted on our custom LS1046 hardware. When we read RSTRQSR we get the following:

md 1ee00C8

01ee00c8: 00480000 00000000 00000000 00000000

If I'm ordering my bytes correctly that means:

MBEE_RR (Multi-bit ECC reset request) and

SRDS_RST_RR (SerDes reset event. Occurs if any enabled SerDes PLL does not lock.)

Can anyone confirm that my decoding of this is correct, and suggest what might cause MBEE_RR? I'm unsure where to start looking with this.

Thanks

[SimonRo · Accepted solution]

We fixed the issue - we had got our values for SRDS_PLL_PD_S1 and SRDS_PLL_PD_S2 wrong - the reference manual is a bit confusing for these. Once we sorted that out the error went away.

[SimonRo]

I've powered down SERDES by setting SRDS_PLL_PD_S1 and SRDS_PLL_PD_S2 to 0.

My RCW now looks like this:

       00000000: 0c150010 10000000 00000000 00000000
       00000010: 11330559 40000012 60040000 c1000000
       00000020: 00000000 00000000 00000000 10038ffe
       00000030: 20124000 04261301 00000096 00000001

But still RESET_REQ_B is asserted:

=> md 1ee0000
01ee0000: 7f7f7720 0000004f 00000000 00000000     w..O...........
01ee0010: 00000000 00000000 00000000 00000000    ................
01ee0020: 00000000 00000000 00000000 00000000    ................
01ee0030: 00000000 00000000 00000000 00000000    ................
01ee0040: 00000000 00000000 00000000 00000000    ................
01ee0050: 00000000 00000000 00000000 00000000    ................
01ee0060: 00000000 00000000 00000000 00000000    ................
01ee0070: 00000000 00000000 00000000 00000000    ................
01ee0080: 00000000 00000000 00000000 00000000    ................
01ee0090: 00000000 00000000 00000000 00000000    ................
01ee00a0: 00000000 10010787 40000000 00000000    ...........@....
01ee00b0: 00000000 00000000 00000000 00000000    ................
01ee00c0: 00400000 00000000 00480000 00000000    ..@.......H.....
01ee00d0: 00000000 00000000 00000000 00000000    ................
01ee00e0: 00000000 00000000 00000000 00000000    ................
01ee00f0: 00000000 00000000 00000000 00000000    ................

Which I think is: SRDS_RST_RR (SerDes reset event. Occurs if any enabled SerDes PLL does not lock.)

I'm wondering why I see this if SERDES is powered down?

Thanks

[LFGP]

Dear @SimonRo,
could you please appoint in what step of the "4.4.1 Power-on reset sequence " you are seeing the issue?
or is it happening after booting up ends?
I need more info in order to understood what could be happening.