LS1046 PTP EXTTS configuration.

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LS1046 PTP EXTTS configuration.

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Oleksandr1
Contributor I

I am going to use External Time Stamps for PTP timer on LS1046A CPU. Now I need to configure an input pin to be used as a TSEC1588_TRIG_IN1. According to "LS1046A Reference Manual" I need to modify the RCW[EC2] = 010. So I introduced the following change to my 'rcw' source file:

...
#include <ls1046a.rcwi>                                                 
+ EC2=2
...

Beforehand these pins controlled by RCW[EC2] (EC2_RX_DV, EC2_RXD[0], EC2_RXD[1], etc )were used to communicate with RGMII PHY and the voltage they used was 1.8v.

What voltage (3.3v or 1.8v) can I apply to TSEC1588_TRIG_IN1 pin after setting RCW[EC2] to '010' ?

Can I enable the internal pull-up resistor somehow on TSEC1588_TRIG_IN1 pin?

 

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r8070z
NXP Employee
NXP Employee

According to the LS1046A datasheet this pin buffer powered by LVDD and LVDD can be 1.8V or 2.5V. LVDD based receivers are simple CMOS I/O circuits and satisfy appropriate LVCMOS type specifications. The datasheet Table 3 “Absolute maximum ratings for input signal voltage levels” says that Max DC V input range is GND to (LVDD x 1.1). The datasheet section “IEEE 1588 DC electrical characteristics” provides the VIH/VIL (Input high/low voltage).

The internal pull-up resistor cannot be enabled after PORESET is negation.

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2,716件の閲覧回数
r8070z
NXP Employee
NXP Employee

According to the LS1046A datasheet this pin buffer powered by LVDD and LVDD can be 1.8V or 2.5V. LVDD based receivers are simple CMOS I/O circuits and satisfy appropriate LVCMOS type specifications. The datasheet Table 3 “Absolute maximum ratings for input signal voltage levels” says that Max DC V input range is GND to (LVDD x 1.1). The datasheet section “IEEE 1588 DC electrical characteristics” provides the VIH/VIL (Input high/low voltage).

The internal pull-up resistor cannot be enabled after PORESET is negation.

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