LS1046 IFC chip select 2 TRAD value has no effect

[micha]

Hello,

we have an own LS1046 board, with an SRAM on IFC chip select 2,

we are not able to control OE low cycle, any value of TRAD in FTM1 register has no effect, the low cycle is always just one IFC-CLOCK (44ns), which is too slow for the SRAM

the TRAD field works well for CS1 or CS3, but there are other components connected

(CPLD, FPGA)

Is that an known silicon issue ?

or  ... what is different to CS2 ??

we tried exact the same register settings on all CSn, just different address spaces,

Thanks for any hints

Regards,

Mike

=> md.l 1530000
01530000: 00000401 00000000 00000000 00000000 ................
01530010: 00000000 00000000 00000000 85000070 ............p...
01530020: 00000000 00000000 85000060 00000000 ........`.......
01530030: 00000000 85000170 00000000 00000000 ....p...........
01530040: 00000000 00000000 00000000 00000000 ................

015301f0: 0e000ee0 001f000e 1f00200e 00000000 ......... ......
=>
01530200: 00000000 00000000 00000000 00000000 ................
01530210: 00000000 00000000 00000000 00000000 ................
01530220: 0e000ee0 001f000e 1f00200e 00000000 ......... ......
01530230: 00000000 00000000 00000000 00000000 ................
01530240: 00000000 00000000 00000000 00000000 ................
01530250: 0e000ee0 001f000e 1f00200e 00000000 ......... ......

[ufedor]

Assuming that 22-/25-bit address mode is used check that IFC_RB2_B is pulled high through a 1 kΩ resistor to OVDD.

[micha]

Thank you for the hint,

I tried 1K pullup to OVDD, the RB2 is stable high during access, nothing else is connected.

unfortunately it has no effect, OE low cycle is just one IFC clock cycle.

and I'm wondering why I need an external RB input when I work with internal TE ?

anyway, it has something to do with RB2, 

when I set the RCW , IFC_GRP_A_BASE[412-413] to 01, which means RB2, RB3 pins are GPIOs, then I can control OE low time via TRAD field, and SRAM works

but in that case I loss RB3 which I need for CPLD in GASIC mode,

we work in 25-bit address mode

I appreciate any comments 

Regards,

Mike

[ufedor]

> we work in 25-bit address mode

Which exactly cfg_rcw_src is used (value of the DCFG_CCSR_PORSR1)?

Please provide U-Boot log as text attachment.

[micha]

currently we boot from SD card, because we have a bug in parallel NOR flash,

we want to boot from flash after redesign

Regards,

Mike

[micha · Accepted solution]

I could go back to check the issue again, 

the 1K pull up helps, the patch was wrong done

Thanks again for help,

Mike

[micha]

sorry, I meant,

44ns is too fast for a 60ns SRAM