LS1046 External MDIO max Frequency

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LS1046 External MDIO max Frequency

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sanspepin
Contributor II

Hi

I would like a confirmation of the LS1046 external MDIO max frequency. Some document seem to reference a max frequency to 2.5MHz. (That seem like a typo)

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Others documents ( like QorIQ LS1046A Data Path Acceleration Architecture) mention that the external MDIO support higher frequency.

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The Ethernet Phy that we use support up to 12 MHz

What is the maximal frequency for external MDIO? What is the recommended  value for the EHOLD and MDIO_HOLD for that frequency?

Please confirm. thanks

 

 

 

 

 

 

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Hector_Villarruel
NXP TechSupport
NXP TechSupport

Hello @sanspepin 

Hope this post finds you well,

Please refer to the information displayed at section 3.10.7.1.2 EMI1 AC timing specifications at the MDC frequency field from the QorIQ LS1046A, LS1026A Data Sheet, Rev. 4, 06/2020. 

I would like to mention their respective note:

"This parameter is dependent on the Ethernet clock frequency. The MDIO_CFG[MDIO_CLK_DIV] field determines the clock frequency of the MgmtClk Clock EC_MDC."

Referring to the information located on 6.4.3.4.1 MDIO Configuration Register (MDIO_CFG) from the QorIQ LS1046A Data Path Acceleration Architecture (DPAA) Reference Manual, Rev. 0 at field "MDIO_CLK_DIV"

For internal MDIO/MDC accesses, only default MDIO_CLK_DIV value should be used regardless of FMan frequency value. If MDIO_CLK_DIV is programmed with a different value than default setting, then for internal MDC accesses the upper resulting MDC frequency should not exceed 10 MHz

Regarding your questions:

Due to this information, I would like to confirm you that such signal should not exceed 10Mhz.

In addition, 

Regarding the value for the EHOLD and MDIO_HOLD,
Please refer to the MDIO_HOLD field from the section 6.4.3.4.1 MDIO Configuration Register (MDIO_CFG) from the QorIQ LS1046A Data Path Acceleration Architecture (DPAA) Reference Manual, Rev. 0.

Have a great day.

Best Regards,

Hector Villarruel.

 

 

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