Hi,
I am using the CW TAP module along with the CWH-CTP-CTX10-YE on my LS1046 design.
For a newer design, I need to add in a buffer between the TAP and the LS1046 processor.
Can you please provide me the logic levels so that I can ensure it will meet the specification?
This interface is running at 1.8V.
Thanks!
Hello matthej!
We only have this document with that information but it is not that specific because the CodeWarrior Tap automatically supports system voltage levels from 1.2v to 3.3v
CodeWarrior<sup>®</sup> Tap - Fact Sheet (nxp.com)
Best regards!
Hello matthej!
In the next link you can download the datasheet for the LS1046.
# Layerscape® 1046A | NXP Semiconductors
In the page 51 you can see the table 4 for recommended operating conditions and for more specific information about the logic levels on this chip you can consult the page 151 for GPIO DC electrical characteristics
Best regards!
In the following link you can find the "CodeWarrior TAP Probe User Guide" in which you can find specifications and steps to configure the TAP Probe and be able to perform and view device information.