LS1043a clock configuration issue?

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LS1043a clock configuration issue?

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Might-Lee
Contributor III

Platform: LS1043a target board

LSDK: lsdk2012

QSPI FLASH: S25FS512SDSMFI011


I generated the SD boot with the LSDK version lsdk2012, but the figure 1 below shows the baud rate was changed when it ran to BL31. The baud rate is correctly output at 115200 before BL31, then I measured the waveform it became 178000 after BL31. The figure 2 below shows the clock configuration data is incorrect.(The correct clock configuration is figure 3.) Is there anything I can modify?

MightLee_0-1627493098617.png

MightLee_1-1627493108652.png

MightLee_0-1627917201485.png

 

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Might-Lee
Contributor III

I found the root cause.

In the config setting of LS1043aQDS CONFIG_SYS_CLK_FREQ and CONFIG_DDR_CLK are obtained by using get_board_sys_clk() and get_board_ddr_clk().

LS1043aRDB sets the value directly at 100M.

After correcting this part in LS1043aQDS, the clock configuration is correct.

MightLee_0-1628266920926.png

 

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yipingwang
NXP TechSupport
NXP TechSupport

In atf source code, please define the following in plat/nxp/soc-ls1043/ls1043aqds/platform_def.h

/* UART related definition */
#define NXP_CONSOLE_ADDR NXP_UART_ADDR
#define NXP_CONSOLE_BAUDRATE 115200

In u-boot source, please define the following in include/configs/ls1043a_common.h.

#define CONFIG_SYS_NS16550_CLK (get_serial_clock())

Modify to

#define CONFIG_SYS_NS16550_CLK 115200

 

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Might-Lee
Contributor III

After I modified as you suggested, the baud rate value measured became to around 12M and it's over UART spec to output data.

Then I modified “#define CONFIG_SYS_NS16550_CLK 115200” to “#define CONFIG_SYS_NS16550_CLK (get_serial_clock())” , the baud rate retrieved 178000.

 I think the root cause is the core frequency is changed from 1600MHz to 1066MHz to affect the baud rate.

How to correct the core frequency to 1600MHz?

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yipingwang
NXP TechSupport
NXP TechSupport

Please customize RCW configuration file packages/firmware/rcw/ls1043aqds/RR_FQPP_1455/rcw_1600_sdboot_qspi.rcw according to your custom board.

Is Sys Clock 100 MHz on your custom board?

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Might-Lee
Contributor III

Yes, system clock is 100MHz on custom board.

BTW, I tested with the same custom RCW and DDR value based on LS1043ardb, the test result below shows the clock configuration is correct, but not for LS1043adqs.

Is there any difference between ls1043aqds and ls1043ardb on clock configuration?

MightLee_1-1628095084097.png

 

MightLee_2-1628095090298.png

 

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yipingwang
NXP TechSupport
NXP TechSupport

Please run the following command to get the difference.

vimdiff packages/firmware/rcw/ls1043aqds/RR_FQPP_1455/rcw_1600_sdboot_qspi.rcw packages/firmware/rcw/ls1043ardb/RR_FQPP_1455/rcw_1600_sdboot.rcw

rcw_1600_sdboot_qspi.rcw enables QSPI in SD boot.

rcw_1600_sdboot.rcw enables IFC in SD boot.

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Might-Lee
Contributor III

The result below shows no difference.

Is it a bug for LS1043aqds on clock configuration? If yes, how to correct it?

MightLee_0-1628178721175.png

 

.

 

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yipingwang
NXP TechSupport
NXP TechSupport

It seems that you used different RCW file in packages/firmware/rcw/ls1043aqds/RR_FQPP_1455/rcw_1600_sdboot_qspi.rcw provided in LSDK 20.12.

Please use the attached RCW file from LSDK20.12.

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Might-Lee
Contributor III

I currently tested on our custom board, so I should use custom RCW file rather than LS1043aQDS. It's weird that I generated the SDboot image with the same custom RCW file based on LS1043aRDB in LSDK2012 and LS1043aQDS in LSDK2012 separately. After SDboot on our custom board, I found the SDboot file by using LS1043aRDB in LSDK2012 generated works correctly, but not for LS1043aQDS in LSDK2012.
Apart from the RCW/DDR file, I didn't modify anything. Why the SDboot file generated from the LS1043aQDS in LSDK2012 works incorrectly?

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Might-Lee
Contributor III

I found the root cause.

In the config setting of LS1043aQDS CONFIG_SYS_CLK_FREQ and CONFIG_DDR_CLK are obtained by using get_board_sys_clk() and get_board_ddr_clk().

LS1043aRDB sets the value directly at 100M.

After correcting this part in LS1043aQDS, the clock configuration is correct.

MightLee_0-1628266920926.png

 

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