LS1043 DDR DQS vs DQ Calibration

[lingjun]

Hi,
I am running QCVS DDR 1D margin test on my board, and I am confused about how this test runs internally. My questions are:

Q1: The 1D margin test sweeps the strobe signal in the data eye for each byte lane. How is it achieved? I don't see any configuration register for adjusting the data eye timing for each byte lane. Is this configuration register reserved and not shown to users?

Q2: Will centering the data eye for each byte lane be automatically done in the DDR initialization flow without any customer register configuration ?

[LFGP · Accepted solution]

Dear @lingjun ,

Regarding your questions:

Q1. The tool “sweeps the strobe signal in the data eye for each byte lane, using small timing steps”, this sweep happens after the controller has already initialized using its normal internal calibration sequence.

NXP does not expose these  DQS delay registers in the memory map, they are internal PHY registers accessed by the controller firmware used during training and by the QCVS validation tool.

Q2. Yes, the DDR controller performs automatic read/write leveling and strobe centering. The QCVS margin test uses this calibrated specific value timing as the reference point.

Best regards

LFGP

[lingjun]

Dear LFGP:

 thanks your reply, It really helpful to me.

But in margin test in my board occur another wired question.  From  QCVS FAQ Guide.pdf the  bright green cells means which the controller  automatic choose strobe center point. My test result show below, the Lane 0~2  have the bright green cells,but Lane 3 don't have bright green cell.

Q1: Does the controller choose strobe point fall into the failing regions cell and so no bright green shown in Lane3?

Q2: can your give some suggestion how to deal with the Lane3 issue? 

thanks very much.