I believe there is a power sequencing conflict between the LS1028A datasheet and the PMIC datasheet.
The LS1028A datasheet shows the power sequencing requirements as follows.
The PMIC for the LS1028A (34VR500V9) shows the following sequence.
The 1.35V and 1.0V (VDD) are out order between the two datasheets.
We are considering implementing a custom power scheme not utilizing the NXP PMIC. What order is correct?
The power sequence described in the data sheet is correct.
Note that 'Step 3' of the power sequence contains following remark:
"System with DDR4 memory (1.2V): G1VDD (XVDD, AVDDSD1_PLL1 and AVDD_SD1_PLL2 can be powered up in any step)". In other words, 1.35V order is relaxed in DDR4 case, so no conflict.