Hello,
From the data sheet timing specification in Table 13 (pg. 75), does that means POR configs has to follow all requirements below?
- Valid for 4 SYSCLK (40 ns) before the rising edge of PORESET_B
- Valid for 2 SYSCLK (20 ns) after the rising edge of PORESET_B
- Tri-state within 5 SYSCLK (50 ns) of the rising edge of PORESET_B
Note: I assume SYSCLK is 100 MHz.
Data Sheet Table 13:
If that is true, the LS1028A Reference Design Board CPLD seems violating the maximum valid-to-high impedance time requirement.
I ran the simulation using the provided code, and the CFG_DRV (signals control POR configs) tri-state after 6 HOT_CLK(25MHz) (240 ns) after the rising edge of PORESET_B (see waveform screenshot below. Signal relevant to this question is in color magenta).
Is there any reason why the CPLD holds POR configs signals longer than the maximum time on data sheet? Or did I misunderstand the meaning of the “maximum valid-to-high impedance time” from the data sheet? Thanks.
