LS1023A IFC Integrated Flash Controller can't find SRAM Base address

[Salman_tahir]

Hi, I am working on LS1023A's peripheral  IFC (Integrated Flash Controller)

Question: How can be found the SRAM base address used by the IFC for the NAND Flash device?

                I am interfacing MT29F8G08ABBCAH4 with IFC.   

[Salman_tahir]

Thanks @yipingwang 

[Salman_tahir]

Thanks @yipingwang

I have the following ifc node in the DTS file

&ifc {
status = "okay";
#address-cells = <2>;
#size-cells = <1>;
/* NAND Flashes, SRAM and FPGA on board */
//ranges = <0x0 0x0 0x00000006 0x20000000 0x40000000
// 0x1 0x0 0x0 0x60000000 0x00080000
// 0x2 0x0 0x0 0x70000000 0x00020000>;
ranges = <0x0 0x0 0x0 0x70000000 0x10000000
0x1 0x0 0x0 0x60000000 0x00080000
0x2 0x0 0x0 0x60100000 0x00020000>;

nand@0,0 {
compatible = "fsl,ifc-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0 0x0 0x10000000>;
};

sram@1,0 {
compatible = "renesas,rmlv0416egsb";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x1 0x0 0x00080000>;
};

fpga: board-control@2,0 {
compatible = "nec,gcd-cp30-fpga";
reg = <0x2 0x0 0x0020000>;
};
};

Its mean NAND device is attached with CS0 and NAND_BASE base address is 0x70000000

is this understanding correct?

[yipingwang · Accepted solution]

Yes, correct.

[yipingwang]

The base address of the SRAM buffer is mapped by the base address of the corresponding NAND FCM bank (chip-select) by setting IFC_CSPRn[BA].

You could refer to u-boot definition include/configs/ls1043ardb.h.

#define CONFIG_SYS_NAND_BASE 0x7e800000
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE

#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_NAND \
| CSPR_V)
#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)

#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR