LS1021a CPLD Reset

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LS1021a CPLD Reset

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jiye
Contributor V

Hi,

Can anyone explain this below:

pastedImage_1.png

(1)Does this mean that every time when there is a hreset_b_18 event let's say 1, then all variable relates to this signal will get reset to 1 as well? such as pcie interface or DDR?

(2) If my standalone ls1021a board does not have hreset_b_18 signal anymore how am I able to reset such as pcie or DDR?

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ufedor
NXP TechSupport
NXP TechSupport

1) Yes, the HRESET_B timing makes it convenient to use this signal as reset for DDR SDRAM and PCIe.

2) Mostly HRESET_B is used because of DDR SDRAM - refer to the AN5097 - Hardware and Layout Design Considerations for DDR4 SDRAM, Appendix B DRAM reset signal considerations. If CKE is not used in the design it is possible to use PORESET_B as global reset.

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jiye
Contributor V

(2) Can you explain a little bit more about the CKE? I do have an active high CKE enable pin from my atmega328 which use to drive the D1_MCKE0 pin low on the LS1021A, if I do have this pin my question is do I need to follow a certain logic for the reset. For example do I need to wait for assertion event of PORESET_B to trigger the DDR reset. what is the DDR control signal assertion logic suppose to be ?

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ufedor
NXP TechSupport
NXP TechSupport

Please refer to the AN5097.

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