Hi Pavel,
I have the following follow up questions. Please help answer these. In advance, thank you.
1) App note AN5097 states:
• Bit-swap is only allowed within a nibble.
• Bit-swap across two nibbles is not allowed.
Does this note refer to just x4 memory configurations (where there is one DQS pair per 4-bits)? Or does it also refer to x8 configurations (where there is one DQS pair per 8-bits)?
2) In app note AN5097 it states "17 For QorIQ products with DDR3L and DDR4 memory options, there is an external VREF pin available for DDR3L mode. When DDR4 mode is used the external VREF pin needs to be grounded."
To which pin is it referring as I don't see an equivalent comment in the reference manual?
3) In an earlier email it was suggested that the TA_BB_RTC be driven from a 1.8V device. However, I am using TA_BB_RTC as my clock input which is powered from TA_BB_VDD (which is a 1V supply), surely the I/O voltage to that pin should be a maximum of 1V? Or is the pin tolerant to a higher voltage? Where in the datasheet does it show the recommended maximum voltage driving pin R6?
4) It looks to me like there is an inconsistency in the datasheet.
Page 20 says MDC/MDIO are related to L1VDD.
Page 61 says that Ethernet Management Interface is powered by LVDD.
Page 92 says that the MDC/MDIO pins are available on LVDD and L1VDD.
Could you clarify which comment is correct, and perhaps get the datasheet corrected.
5) It looks to me like there is another inconsistency in the datasheet.
Page 51 says DVDD is 1.8 V ± 90 mV
The schematics for LS1021A-IOT and TWR-LS1021A-PB both have DVDD connected to 3.3V I/O.
Pin J2 is a good example.
Could you tell me the real voltage range for DVDD.
6) Could you please confirm that the power draw highlighted in yellow in the attached is the total power drawn by both the AVDD_SD1_PLL1/2 pins, and not per PLL pin.
