We have considered LS1012A for one of the product where we would like to use LS1012A in EP mode of PCIe interface. we have got confirmation from one of the FAE that it's(LS1012A)'s Linux PCIe EP mode driver will be available by October month and we have considered our project timelines accordingly.
Now apart from this we have one question of how we can get notification/interrupt whenever HOST writes any data to any of the BAR memory (memory of LS1012A mapped to any BAR). Is there any way to know that HOST as done the write operation?
Please check attached file has block diagram of our application.
Our plan is to use LS1012A as bridge chip between PCIe and USB for USBTMC functionality.
There will be a test & measurement device which will running on Windows 10 with Intel processor.
LS1012A will running on Linux (Yocto build) and will connect with test & measurement device over PCIe as Endpoint device.
One can connect LS1012A(as USB client-Gadget) over USB with USER PC for USBTMC operation.
So LS1012A work as bridge chip between User system and Test & measurement device.
LS1012A PCIe Endpoint driver Requirement:-
- N number of BAR will be configured/set based on requirement
- BAR will be configured with specific memory size
- BAR memory addresses will be accessible for read & write operations
Custom USBTMC gadget driver Requirement:-
- 4 Endpoint will required 1 for Control, 1 for BULK IN, 1 for BULK OUT & 1 for Interrupt IN
- Access same BAR memory(of EP mode driver) to perform read write operation based on BULK IN & BULK OUT request, by avoiding any mem copy operations.
Linux Daemon + Custom char driver Requirement:-
- This will do required configuration for USBTMC and PCIe driver
1. Is LS1012A good option for above requirement? Do you see any limitations?
2. LS1012A need to boot and initialize PCIe Endpoint as soon as possible in order to compliance with Windows 10 system(Intel) BIOS requirements i.e. any connected PCIe device should be detectable by PCIe bus of Intel within 100ms.What is your suggestion to achieve this i.e. optimize a boot time and make PCIe ep ready to be able to detect by BIOS of intel within 100ms.
3. We want to access PCIe BAR memory from USBTMC gadget driver to perform USBTMC read write operation. Idea behind this is to get physical address of the any BAR memory and use same buffer to perform USB transactions in custom Gadget driver.
4. When USBTMC BULK IN request receive from User system we need to provide requested data back to User system. So once data filled in PCIe BAR memory by test & measurement device we need some kind of notification to know data is available in BAR memory and send back to User system via USB gadget driver. PCIe works as requester and completer so it means Endpoint driver request test & measurement device to write data in BAR memory and once this done test & measurement send completion to Endpoint driver?
1) No obvious limitations is seen.
2) It is possible to perform necessary SoC initialization steps within 100 ms.
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