LA1224RDB-B FreeRTOS PCIe Driver RC-EP

[flappy]

I am trying to realize communication of LA12xx devices via PCIe link. The LA12xx (1) PCIe RC controller is connected to the PCIe EP controller of the LA12xx controller (2) using an M4 board that supports PCIe Gen3 speed (the LA1224-RDB-B board is used).
(BSP Appendix D).
I set the appropriate DIP switches. Built FreeRTOS with PCIe Driver BSP 2.4.
The link does not go up. LTSSM in Poll_comp 0x3 state on both RC and EP.
SW6[3] = 1 SW4[5-7] = 0x2 (010) SW5[5] = 1 RC 0 EP.
What can be the reason? Same code and wiring diagram, but EP - Xilinx FPGA - get link-up.

[flappy · Accepted solution]

The problem was the circuitry part. Thank you all for the answers!

[Oswalag]

Hello.

Please share a block diagram of the connections, also try to connect any other device as PCIe EP to discard any issue from the RC configuration side.

Regards

[flappy]

Good afternoon, thank you for your response!

I connected as EP device - Xilinx Kintex FPGA and got successful connection. So I rule out the problem on the RC device side.
I am also attaching a schematic block diagram.

Thank you for your help.

[Oswalag]

Hello,

Something doesn't make sense in your block diagram:

 

The LA1224 only have 2 pcie controllers, pcie1 only can be configures as EP so how are you connecting the LX2160A as RC to the LA as EP and also connecting the LA as RC(pcie2 controller) to the same LA EP(pcie1)?

[flappy]

Hello!

We are connecting PCIe2 on LA(1) as RC to PCIe2 on LA(2) initialized as EP. We make the connection according to Appendix D of BSP 3.0.
In the diagram, the ports associated with the LX are highlighted in black on each RDB. (ignore the color of the arrows).

Settings DIP-Switch:

On LA1 SW5[5]=1.(RC)
On LA2 SW5[5]=0.(EP)

SW6[3]=1 on both boards.(SD_MUX_SEL).

SW4[5-7]=010 ( corresponds to x4, CFG_SD_PRTCL=2).