Interrupt low time for ARMv8-A53

キャンセル
次の結果を表示 
表示  限定  | 次の代わりに検索 
もしかして: 

Interrupt low time for ARMv8-A53

1,638件の閲覧回数
pro-supportengi
NXP Employee
NXP Employee

I want to now what is the minimum low time required for the ARMv8-A53 interrupt to detect as a valid interrupt.

Pls guide with proper reference.

For example, the ethernet driver for the LS1043ARDB and/or toggling a GPIO for an interrupt?

ラベル(1)
0 件の賞賛
返信
2 返答(返信)

1,429件の閲覧回数
r8070z
NXP Employee
NXP Employee

Have a great day,

The LS1043A interrupt controller (GIC) inputs are asynchronous to any visible clock. GIC inputs are required to be valid for at least 3 SYSCLKs to ensure proper operation.

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

0 件の賞賛
返信

1,429件の閲覧回数
pro-supportengi
NXP Employee
NXP Employee

What is the best and worst case latency for interrupts on the LS1043A?  Latency between the occurrences of the interrupt and the start of the ISR.

0 件の賞賛
返信