How to enable error injection on LS1043A DCache

[aross]

I am trying to test error handling for DCache ECC errors in bare-metal (running at EL3) on a LS1043ARDB.

If I set CPUACTLR_EL1.L1DEIEN (bit[6]) and then write a cacheable location, nothing seems to happen.

The CPUMESSR doesn't change, nor is there an abort, etc.

I have also tried L2 (L2ACTLR[29]) and caused an eviction from L1.

I can see the data is in the cache by reading the cache RAM.

I feel like I am missing some other enable somewhere?

[ufedor]

You need to explicitly read(via LDR instruction) that cacheline again after the error is injected into corresponding caches(triggered by the previous write). CPUMERRSR or L2MERRSR can record the error information once the injected error line is read again.

[aross]

I looked closer at the data via reading the cache RAM and noticed it looks like it did flip 2 bits in the data. 

But didn't report any error. So maybe there's an enable for the cache ECC?