Generating DDR parameters using Code Warrior

[pb3]

Hi,

I'm trying to figure out how to properly generate DDR parameters to use in TFa for LS1028a.

In TFA in ddr_init.c for the LS1028a I can find something like this

#ifdef CONFIG_STATIC_DDR
const struct ddr_cfg_regs static_1600 = {
	.cs[0].config = U(0x80040422),
	.cs[0].bnds = U(0xFF),
	.sdram_cfg[0] = U(0xE50C0004),
	.sdram_cfg[1] = U(0x401100),
	.timing_cfg[0] = U(0x91550018),
	.timing_cfg[1] = U(0xBAB40C42),
	.timing_cfg[2] = U(0x48C111),
	.timing_cfg[3] = U(0x1111000),
	.timing_cfg[4] = U(0x2),
	.timing_cfg[5] = U(0x3401400),
	.timing_cfg[7] = U(0x23300000),
	.timing_cfg[8] = U(0x2114600),
	.sdram_mode[0] = U(0x3010210),
	.sdram_mode[9] = U(0x4000000),
	.sdram_mode[8] = U(0x500),
	.sdram_mode[2] = U(0x10210),
	.sdram_mode[10] = U(0x400),
	.sdram_mode[11] = U(0x4000000),
	.sdram_mode[4] = U(0x10210),
	.sdram_mode[12] = U(0x400),
	.sdram_mode[13] = U(0x4000000),
	.sdram_mode[6] = U(0x10210),
	.sdram_mode[14] = U(0x400),
	.sdram_mode[15] = U(0x4000000),
	.interval = U(0x18600618),
	.data_init = U(0xdeadbeef),
	.zq_cntl = U(0x8A090705),
	.clk_cntl = U(0x2000000),
	.cdr[0] = U(0x80040000),
	.cdr[1] = U(0xA181),
	.wrlvl_cntl[0] = U(0x8675F605),
	.wrlvl_cntl[1] = U(0x6070700),
	.wrlvl_cntl[2] = U(0x0000008),
	.dq_map[0] = U(0x5b65b658),
	.dq_map[1] = U(0xd96d8000),
	.dq_map[2] = U(0),
	.dq_map[3] = U(0x1600000),
	.debug[28] = U(0x00700046),
};

unsigned long long board_static_ddr(struct ddr_info *priv)
{
	memcpy(&priv->ddr_reg, &static_1600, sizeof(static_1600));
	return ULL(0x100000000);
}

#else

and also something like this:

/* DDR model number:  MT40A1G8SA-075:E */
struct dimm_params ddr_raw_timing = {
	.n_ranks = U(1),
	.rank_density = ULL(4294967296),
	.capacity = ULL(4294967296),
	.primary_sdram_width = U(32),
	.ec_sdram_width = U(4),
	.rdimm = U(0),
	.mirrored_dimm = U(0),
	.n_row_addr = U(16),
	.n_col_addr = U(10),
	.bank_group_bits = U(2),
	.edc_config = U(2),
	.burst_lengths_bitmask = U(0x0c),
	.tckmin_x_ps = 750,
	.tckmax_ps = 1900,
	.caslat_x = U(0x0001FFE00),
	.taa_ps = 13500,
	.trcd_ps = 13500,
	.trp_ps = 13500,
	.tras_ps = 32000,
	.trc_ps = 45500,
	.twr_ps = 15000,
	.trfc1_ps = 350000,
	.trfc2_ps = 260000,
	.trfc4_ps = 160000,
	.tfaw_ps = 21000,
	.trrds_ps = 3000,
	.trrdl_ps = 4900,
	.tccdl_ps = 5000,
	.refresh_rate_ps = U(7800000),
	.dq_mapping[0] = U(0x16),
	.dq_mapping[1] = U(0x36),
	.dq_mapping[2] = U(0x16),
	.dq_mapping[3] = U(0x36),
	.dq_mapping[4] = U(0x16),
	.dq_mapping[5] = U(0x36),
	.dq_mapping[6] = U(0x16),
	.dq_mapping[7] = U(0x36),
	.dq_mapping[8] = U(0x16),
	.dq_mapping[9] = U(0x0),
	.dq_mapping[10] = U(0x0),
	.dq_mapping[11] = U(0x0),
	.dq_mapping[12] = U(0x0),
	.dq_mapping[13] = U(0x0),
	.dq_mapping[14] = U(0x0),
	.dq_mapping[15] = U(0x0),
	.dq_mapping[16] = U(0x0),
	.dq_mapping[17] = U(0x0),
	.dq_mapping_ors = U(0),
	.rc = U(0x1f),
};

It seems that the static_1600 is not being used during LS1028 build, instead ddr_raw_timing structure is being used.

I tried to generate the similiar structure using CodeWarrior but for some reason it generates ddr_cfg_regs structure not the ddr_raw_timing structure.

Why is that?

How can I generate ddr_raw_timing structure?

What's the difference between them?

Which one should I use?

[Hector_Villarruel]

Hello @pb3 

Hope this post finds you well,

Please note that on ddr.c, raw timing methods is used. In QCVS(DDRv project), after optimization and validation with DDRv tool, you could get the final DDR raw timing parameters in the properties panel in QCVS project, you  could use these parameters in u-boot to configure DDR controller with raw timing parameters.

Are you using the CodeWarrior QCVS tool?

Is this a custom board ?

If so, does the board passes the DDR validation test?

Have a great day.

We will be aware for your kind reply.

BR,

Hector

[Hector_Villarruel]

Hello @pb3 

This post is to inform you that we acknowledge the receipt of your case,
I Keep working on the solution on this case.
I’ll keep you informed on the process,

BR,

Hector