We are trying to customize code from U-Boot for our application. In particular, we are currently looking to add baremetal support for the SEC Accelerator, and for this we are using the Job Ring interface.
However, we are finding the following values in JRSTAR, JRINTR registers, after writing to the Input Ring Jobs Added Register :
JRSTA : 0x1E010060 , indicating error reading input ring address (according to error table in SEC Ref Manual)
JRINTR : 0x02010000, indicating error writing status to output ring (according to register definition in SEC Ref Manual)
Our Input & Output Job Ring (JR0) Base Addresses are located in OCRAM. Cache support is not enabled. We have tried both BE & LE writes to the JR with the address of the Job Descriptor, however we obtain the same errors, and cannot generate any other error codes.
Would appreciate it if anyone can help us on what we may be missing here.
Solved! Go to Solution.
Thanks for pointing us in the right direction. Enabling the TZ bit in JR ICID Register worked for us.
Also, in the U-Boot source, after a job is completed by the SEC, is it necessary to call jr_sw_cleanup? Seems like the code for dequeuing jobs from the ring does not clear the older jobs in the jobring structure automatically.