ESD testing failure for LS1043A

[chithanhhoang]

Hi,

During our early ESD test prior going to the certification, we found our board using LS1043A exhibit several critical issues during ESD tests.

Case 1- The Serdes LaneA connected to Vitesse 8514 seems to transmit error to VSC8514, the VSC8514 still works fine, after ESD hit ethernet outbound packets do not reach into VSC8514, remedy was to reset serdes by detection of failure, I saw similar hack proposed for P1020 back in 2015.

Case 2- Sometime CPU/core seem to stop working, so we enable hw watchdog to reset board to recover.

Case 3- Even with hw watchdog enable, we found hw watchdog stop working as well, i.e. after refresh timeout expiration, the board still hang, no response.

Our hw team is asking what we could do to improve ESD protection to have the LS1043A still working after ESD hit, and what is the official position of NXP with respect to ESD for LS1043A.

I know my posting encompass several issues with respect to ESD, but if anyone designing using LS1043A or NXP has similar ESD problems and if there is, what is the work around?

Many thanks in advance.

Chi-Thanh

[rahul_bhagat]

Hello chithanhhoang,

Is ESD problem related to LS1043A resolved?

if yes, How you resolved this?

Please share your experience.

Best Regards,

Rahul

[chithanhhoang]

Hi Rahul,

Yes, to fix the ethernet issues we reset the serdes laneA from the LS20143A side when seeing the Vitesse phy "unhappy" with the signal it received.

Also the 2nd issue I observed was DPAA engine go crazy on receive after ESD hit, DPAA would not receive frame and drop ethernet frames from the phy, phy is okay.  The fix was to monitor errors rx counters from DPAA, after some threshold, I decide to reset DPAA by a simple interface down/up, I know it looks ugly but the hack fix the issue and allow us to pass certification.

The 3rd issue observed was sometime, an ARM core decided to hang, so I make use of all the 4 watchdogs on the 1043 and assign them to each of the ARM core, this really fix the case where one of the core hang but the rest still work.

I hope this info help.  Cheers.

[chithanhhoang]

Thank you!

We found internally a work around using remaining watchdogs.

[chithanhhoang]

Thanks for the response.

I understand the LS1043A is meeting 2KV HBM and 500V CDM, and there are internal protection circuit to detect and shunt the charge to protect the chip.

However in real life, the chip stops running and the same for watchdog subsystem, it is not very good in term of system level, currently the only way out is to do a reset explicitly to recover the board, this step is not acceptable for ESD certification as there must be no human intervention (the way I understand it). 

We probed the 32khz feeding LS1043A hw watchdog and signal is good but watchdog not responsive, we waited beyond the 60sec and nothing happen.

What can you suggest next? so we can overcome LS1043A is freezing.

[ufedor]

LS1043A was qualified for 2KV HBM and 500V CDM.

Note:

All Speed Critical pins (SerDes, CLKIN, etc) meet Class II JESD22-C101E 250V, all other pins met Class III JESD22-C101E 500V.