LS1028A JTAG Interface Wiring

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LS1028A JTAG Interface Wiring

Contributor I


I have a quite similar question concerning the wiring of the JTAG interface as @Rashmita (her question has not been answered by now): I am working with a custom design board with an LS1028A SoC. We do not have the QiXi board controller on our board. For now we have the TRST_B pin hardwired to the PORESET. Additionally the nRESET (pin 10 of the ARM Cortex JTAG header) is hardwired to PORESET. I can see that the CodeWarrior TAP is resetting the SoC, but connection to the target failes.

So my first question is: To be able to debug via JTAG, the TRST_B pin has to be isolated from nRESET (e.g. via a logic gate), right? In other words: TRST_B must be hardwired to PORESET and nRESET must be able to drive PORESET w/o driving TRST_B as well?

My second question is: On the LS1028ARDB (the reference design board) the signal connected to the SoC's PORESET pin is generated by the CPLD board controller. The JTAG nRESET and PORESET generated by power supply are both input to the board controller that also generates the RCW (i.e. the boot source select). If I want to debug code via JTAG (i.e. using CodeWarrior studio), do I need to set/ suppress the boot source selection via JTATG as well? In other words: Does the JTAG nRESET signal affect other signals than the PORESET in the CPLD?




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Contributor I

UPDATE: The JTAG interface itself seems to be working now. I can read the ID-String. The SoC's CPUs appear in the context list. But I can't access the registers through the DAP (error: CortexA72#0 is not on the JTAG list). Accessing registers through the SAP#0 works for some but finally results into a 'memory access failed at address' error. Has anybody an idea what might cause this problem?

Error message from gdb:

Memory access failed.
Additional error details:
[Failed to write memory at address 0x1f0000004 on core SAP#0.
GTA: error writing memory]

Result of connection diagnostics:

Screenshot 2022-09-02 105404.png

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