Device node for Ethernet

[varada_pavani]

Hi Team,

We are using phy(88E1512) chip in ls2088a based custom board with sgmii interface. Added a device node sgmii in flexbuild_lsdk1809/packages/linux/linux/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi .

&sgmii {
status ="okay";
#address-cells = <1>;
#size-cells = <0>;
phy0@1 {
device_type = "ethernet-phy";
compatible = "marvell,88e1512";
reg = <0x1>;
};
phy1@0 {
device_type = "ethernet-phy";
compatible = "marvell,88e1512";
reg = <0x0>;
};
};

while compiling linux kernel getting the following error.

Error: /home/user/tar/flexbuild_lsdk1809/packages/linux/linux/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi:113.1-7 Label or path sgmii not found
FATAL ERROR: Syntax error parsing input tree

Do i need to add sgmii in any other files? can anyone help me how to add phy details in device tree?

[yipingwang]

Hello VARADA PAVANI,

Please refer to the following definition in fsl-ls2088a-qds.dts.

                  mdio_mux3: mdio@60 {
                                reg = <0x60>;
                                #address-cells = <1>;
                                #size-cells = <0>;

                                mdio0_phy12: mdio_phy0@1c {
                                        reg = <0x1c>;
                                        phy-connection-type = "sgmii";
                                };
                                mdio0_phy13: mdio_phy1@1d {
                                        reg = <0x1d>;
                                        phy-connection-type = "sgmii";
                                };
                                mdio0_phy14: mdio_phy2@1e {
                                        reg = <0x1e>;
                                        phy-connection-type = "sgmii";
                                };
                                mdio0_phy15: mdio_phy3@1f {
                                        reg = <0x1f>;
                                        phy-connection-type = "sgmii";
                                };

                        };

&dpmac9 {
        phy-handle = <&mdio0_phy12>;
};
&dpmac10 {
        phy-handle = <&mdio0_phy13>;
};
&dpmac11 {
        phy-handle = <&mdio0_phy14>;
};
&dpmac12 {
        phy-handle = <&mdio0_phy15>;
};

In addition, please define CONFIG_MARVELL_PHY in Linux Kernel configuration file.

Thanks,

Yiping

[sambit_rout]

Hi Yiping,

We are using the customised ls2088a-rdb board.In our board in serdes 2 (49) we are having a two sgmii.

the sgmii used is marvell 88e1512.
i.e in mdio0 we have phy0 and in mdio1 we have phy0

The following is the dtsi entry for sgmii.

emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000,
* E-MDIO1: 0x1_6000
*/
compatible = "fsl,fman-memac-mdio";
reg = <0x0 0x8B96000 0x0 0x1000>;
device_type = "mdio"; / TODO: is this necessary? /
little-endian; / force the driver in LE mode /

/ Not necessary on the QDS, but needed on the RDB /
#address-cells = <1>;
#size-cells = <0>;
};

emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000,
* E-MDIO2: 0x1_7000
*/
compatible = "fsl,fman-memac-mdio";
reg = <0x0 0x8B97000 0x0 0x1000>;
device_type = "mdio"; / TODO: is this necessary? /
little-endian; / force the driver in LE mode /

#address-cells = <1>;
#size-cells = <0>;
};

The below is the dts entry in fsl-ls2088a-rdb.dts

&emdio1 {
mdio1_phy0: emdio1_phy@1 {
compatible = "marvel,88e1510";
interrupts = <0 2 0x4>;
reg = <0x0>;
phy-connection-type = "sgmii";

};

};

&emdio2 {
mdio1_phy0: emdio1_phy@1 {
compatible = "marvel,88e1510";
interrupts = <0 2 0x4>;
reg = <0x0>;
phy-connection-type = "sgmii";

};

};

&dpmac1 {
phy-handle = <&mdio1_phy1>;
};

&dpmac2 {
phy-handle = <&mdio1_phy2>;
};

We have also enable the the Marvell phy driver in config file.

After compiling the image is flashed and we observe that there no sgmii link created .

We are unable to get the interface for both sgmii in kernel.

Can you help us further with this issue.

Is the compatibility fine or do we need to add anything in dtsi.

Also we are not getting any prints in kernel logs about the driver.

[yipingwang]

Hello Sambit,

Please go to u-boot and type "mdio list" command to show mdio information on your target board.

In u-boot source code, please modify file board/freescale/ls2080ardb/eth_ls2080rdb.c according to your custom board, PHY address is defined in include/configs/ls2080ardb.h.

=> mdio list
FSL_MDIO0:
10 - Cortina CS4315/CS4340 <--> DPMAC1@xgmii
11 - Cortina CS4315/CS4340 <--> DPMAC2@xgmii
12 - Cortina CS4315/CS4340 <--> DPMAC3@xgmii
13 - Cortina CS4315/CS4340 <--> DPMAC4@xgmii
FSL_MDIO1:
0 - Generic 10G PHY <--> DPMAC5@xgmii
1 - Generic 10G PHY <--> DPMAC6@xgmii
2 - Generic 10G PHY <--> DPMAC7@xgmii
3 - Generic 10G PHY <--> DPMAC8@xgmii
=>

Thanks,

Yiping

[sambit_rout]

Hi yipingwang‌

In our custom board there is one 10G and two SGMII, we want the dts changes for sgmii for ls2088ardb board.

We have two PHYs, one in FSL_MDIO0 and FSL_MDIO1. 

When we do mdio list as mentioned above we only get

=>mdio list

FSL_MDIO0:

FSL_MDIO1:

Please help us we it. 

Thanks

Sambit 

[yipingwang]

Hello Sambit,

Please modify the following MDIO MAC(PHY) information in board/freescale/ls2080ardb/eth_ls2080rdb.c according to your custom board.

        switch (srds_s1) {
        case 0x2A:
                wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1);
                wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2);
                wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3);
                wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4);
                wriop_set_phy_address(WRIOP1_DPMAC5, AQ_PHY_ADDR1);
                wriop_set_phy_address(WRIOP1_DPMAC6, AQ_PHY_ADDR2);
                wriop_set_phy_address(WRIOP1_DPMAC7, AQ_PHY_ADDR3);
                wriop_set_phy_address(WRIOP1_DPMAC8, AQ_PHY_ADDR4);

                break;

...

        for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC4; i++) {
                interface = wriop_get_enet_if(i);
                switch (interface) {
                case PHY_INTERFACE_MODE_XGMII:
                        dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
                        wriop_set_mdio(i, dev);
                        break;
                default:
                        break;
                }
        }

        for (i = WRIOP1_DPMAC5; i <= WRIOP1_DPMAC8; i++) {
                switch (wriop_get_enet_if(i)) {
                case PHY_INTERFACE_MODE_XGMII:
                        dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
                        wriop_set_mdio(i, dev);
                        break;
                default:
                        break;
                }
        }

Please modify the following PHY address information in include/configs/ls2080ardb.h.

#define CORTINA_PHY_ADDR1       0x10
#define CORTINA_PHY_ADDR2       0x11
#define CORTINA_PHY_ADDR3       0x12
#define CORTINA_PHY_ADDR4       0x13
#define AQ_PHY_ADDR1            0x00
#define AQ_PHY_ADDR2            0x01
#define AQ_PHY_ADDR3            0x02
#define AQ_PHY_ADDR4            0x03

Then under u-boot read MDIO PHY devices information and check PHY link status.

Thanks,

Yiping

[sambit_rout]

Hi yipingwang‌

We want sgmii to detect and work in kernel level. We have added this in dtsi 

/*&pcs_mdio1 {

              status="okay";

              &pcs_mdio1: phy@1{ compatible = "ethernet-phy-ieee802.3-c45"; status="okay"; interrupts = <0 1 0x4>; reg = <0x00>; phy-connection-type = "sgmii";

                        };

};

We are able to register the phy but unable to get interface, do we need to enable any driver for ethernet mac for interface to be up? 

[yipingwang]

Please check RCW[SRDS_PRTCL_S1] and RCW[SRDS_PRTCL_S2] whether you have configure SGMII Ethernet ports according to your requirement. Please refer to "23.1.2 SerDes 1 and SerDes 2 Protocols" in LS2088 Reference Manual for details.

[souravsambit_r]

Hi Yiping Wang‌

I referred what you suggested and added a node for sgmii in flexbuild_lsdk1809/packages/linux/linux/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts under mdio_mux3 node.

mdio_phy0@1 {
reg = <0x1>;
phy-connection-type = "sgmii";
device_type = "ethernet-phy";
compatible = "marvell,88e1512";
};
mdio_phy1@0 {
reg = <0x0>;
phy-connection-type = "sgmii";
device_type = "ethernet-phy";
compatible = "marvell,88e1512";
};

And enabled MARVELL_PHY in menuconfig.

Now it is compiling successfully without giving error as before.

Can you please confirm if it is a correct way. Addition to this I have configured SerDes pins in RCW using CodeWarrior. Any other thing do i need to add?

Thanks,

Sambit