DDR4 calibration & DQ mapping

[altu]

Good day!

I have a question about DDR DQ mappings in QCVS. I'm trying to calibarte a DDR4 module on our custom ls1046 board. Our custom board have direct mapping to the DDR4 slot(CPU DQ0 connects to DQ0 of DDR4 slot, CPU DQ1 -> DDR4 slot DQ1, and so on up to DQ63).

In QCVS calibration project I successfully read the SPD data from the module and after that I have these DQ mappings:

 

As I understand, these mappings came from SPD data of the DDR4 module and describes the mappings within the DDR4 memory module. And I don't have to change it (because our custom ls1046 board have direct mappings to the DDDR4 slot)? Am I right?

[altu · Accepted solution]

I figure it out - no need to change it in case 1:1 mappings between CPU and memory slot - we must use DDR module mappings, provided by reading SPD .

https://community.nxp.com/t5/Layerscape/LS1046ARDB-DDR-DQ-Mapping/m-p/2180789#M16171 - another topic in the same question