Cortex-A7: Core not responding

[jaroslavdytrych]

Hello All.

We have own board with a LS1020A and there are problems with a linux stability. So we want to run a DDR validation but we have a problem with connecting to the processor using CW QCVS and CodeWarrior TAP.

CCS command output

(bin) 44 % dele a (bin) 45 % config cc cwtap (bin) 46 % ccs::config_chain {ls1020a dap sap2} (bin) 47 % display ccs::get_config_chain Chain Position 0: LS1020A Chain Position 1: CoreSight ATB Funnel Chain Position 2: CoreSight TMC Chain Position 3: CoreSight TMC Chain Position 4: CoreSight TMC Chain Position 5: CoreSight CTI Chain Position 6: CoreSight CTI Chain Position 7: CoreSight CTI Chain Position 8: CoreSight ATB Funnel Chain Position 9: Cortex-A7 Chain Position 10: Cortex-A7 PMU Chain Position 11: Cortex-A7 Chain Position 12: Cortex-A7 PMU Chain Position 13: CoreSight CTI Chain Position 14: CoreSight CTI Chain Position 15: Cortex-A7 ETM Chain Position 16: Cortex-A7 ETM Chain Position 17: DAP Chain Position 18: SAP2 (bin) 48 % ccs::reset_to_debug Cortex-A7: Core not responding

CCS Scan TAP output
(bin) 25 % source IDcode.tclTDO -----         |         * Device 0  IDCODE: 5BA00477  Device: Unknown Device         * Device 1  IDCODE: 16B0001D  Device: FSL LS1 Device rev 2.x         | TDI -----

CW Target Connection output

check_min_version(serverh=0,*version)   api version: 00000004 00000006 available_connections(serverh=0,*count,*cc)   connections: {0,73,0xc0a801db} cc_version(serverh=0,cc_index=0,index=0,*version) config_server(config_reg=0,config_data=0x000027F6) config_chain(serverh=0,cc=0,count=3,*devlist,*generic)   devlist: ls1020a,dap,sap2 reset_to_debug(serverh=0,cc=0)   ERROR(39): Subcore error encountered during multicore operation parse_error_ext(coreh.{serverh=0,cc_index=0,chain_pos=0}, 39)   error: Cortex-A7: Core not responding

Any idea what's wrong?

Maybe incorrect JTAG wiring?

Thanks for any help.

[yipingwang]

Hello Jaroslav Dytrych,

CCS failed at ccs::reset_to_debug, probably there is problem with RCW or JTAG interface hardware design on your target board.

1. Please refer to the section "4.4.6.2 Hard-coded RCW options" in LS1021A Reference Manual to configure your target board to use one hard-coded RCW, then verify your above CCS commands.

2. Please check the hardware design, please download "AN4878, QorIQ LS1021A Design Checklist - Application Note" from QorIQ LS1021A Dual-Core Communications Processor wi|NXP , and refer to "Figure 31. JTAG interface connection" to check your JTAG interface design, especially nRESET pin.

Have a great day,
TIC

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[jaroslavdytrych]

Hello Yiping Wang,

you are right. The problem was incorrect wiring JTAG (nRESET pin) on our target board. Now the problem was solved and the DDR validation tool works.

Thanks for your help.

Regards

Jarda.