Configuring LS1046A board as a PCIe Endpoint

[Matt22]

Hi,

We're trying to design a board using the LS1046A. The board will utilise one of the PCIe bridges as an endpoint (EP), with the remaining two bridges in root-complex mode (RC).

In this article, the document describes how the PCIe REFCLK is connected to the SD2_REFCLK2 of the LS1046ARDB.

Would doing this cause the EP bridge will use the clock provided by SD2_REFCLK2, and the RC bridges will use SD2_REFCLK1?

Also, since our board will be externally powered (not through PCIe), what should we do with the incoming 12v and 3.3v pins of our PCIe connector? Can we leave them unconnected?

Thanks,
Matt.

[yipingwang]

1. Would doing this cause the EP bridge will use the clock provided by SD2_REFCLK2, and the RC bridges will use SD2_REFCLK1?
[NXP]: PLL Reference Clock: RCW[SRDS_PLL_REF_CLK_SEL_S2] selects the refclk for each PLL.
Table 31-2. Supported SerDes2 options shows the PLL mapping.
For example, customer is using 0x5577 protocol.
All lanes will be using PLL2 if operating at gen1/2.
All lanes will be using PLL1 if operating at gen3.
RCW[SRDS_PLL_REF_CLK_SEL_S2] selects the reference clock for each PLL.

Requirement on the clock:
For LS1046A, a spread-spectrum reference clock is permitted for PCI Express, provided that common SerDes reference clock must be used for both link partners. It is recommended that EP works on slot clock. So LS1046A controller as EP uses the clock from slot. Since all three PCIe controllers will work on same PLL so RC will also be running on slot clock in this case.
If customer can ensure that the clock on slot is not spread spectrum enabled then the link partners on both Root Complex may choose their own clock source. If the slot clock cannot be ensured as spread spectrum free then the EP's on the two Roto Complex will also need to use the clock from slot.
Hence we would like to understand at block level how the system is designed and how it is to be deployed? Is it going to sit in an open system or closed system?

2. since our board will be externally powered (not through PCIe), what should we do with the incoming 12v and 3.3v pins of our PCIe connector? Can we leave them unconnected?
[NXP]: They can be left unconnected. GND pins must be connected to GND pins of the controller.