In your CCS log, it failed at "reset_to_debug".
Please make sure SERDES REF CLK is set to 100 MHz, set rcw_src to the hard-coded RCW option matching the board's DIP SW regarding SYSCLK and differential/single-ended clock source
If this problem remains, please check your JTAG hardware interface design.
Please refer to "Figure 18. JTAG interface connection" in the attached application note.
Please refer to "5.28 JTAG pin termination recommendations" in the attached app note.