Clarification on erratum

[rhaas]

I have been reviewing A-008822 in the LS1028A errata (LS1028ACE, Rev2, 2/2023). In A-008822, the workaround asks for a write to the PCIe configurations space offset 8D0h to occur.

I looked in the LS1028A TRM and I was not able to find this register listed.

Is it possible to get the definition of this register. I would like to understand the workaround; in case someone asks.

[Oswalag]

Hello,

There isn't a public description of the register available.

Wording of the erratum A-008822 describes the issue in detail.
As stated, that workaround changes AXI slave response for all error scenarios on non-posted requests from default OKAY to ERROR.

Additional details cannot be provided to the customer because the PCIe IP internals are confidential.

Regards.

[rhaas]

Thank you for the information.

I was wondering if any 'write enable' bit needs to be set before writing this data, similar to MISC_CONTROL_1_OFF.

Thank you