Cannot write data at address 0x80000000

[Johnson_s]

I am confirming the startup of a custom board using the LS1046A. I created the PBL on https://github.com/nxp-qoriq/atf.git to enable booting in QSPI mode. However, when executed, the console message stops at "NOTICE: BL2: Built: [date and time]."

Following advice, I used the QCVS DDR tool to access the DDR, but both read and write failed. Additionally, when I ran [Diagnose Connection] in the [Target Connections] tab, an error was output in the [Test DDR memory access] section: "Cannot write data at address 0x80000000."

What areas need to be modified on https://github.com/nxp-qoriq/atf.git to initialize the DDR for my custom board? Currently, I am creating a PBL based on the LS1046ARDB.

Thanks.

[yipingwang · Accepted solution]

1. First for new DDR bringing up on the a custom board, we suggest the customer use QCVS DDRv tool to do validation and optimization to get the optimized parameters to use them in atf source code.

For QCVS DDRv tool usage, you could refer to the following document.

https://www.nxp.com.cn/docs/en/user-guide/QCVS_DDR_User_Guide.pdf

https://community.nxp.com/t5/Qonverge-Knowledge-Base/DDR-Controller-Configuration-on-LS2085-LS2080-B...

You could use "read from SPD" method to create a QCVS DDR project, then connect to your custom board to do validation to get the optimized parameters and build to generate code ddr_init.c  and use it in ATF source code.

2. Modify atf source code according to your custom board.

Go back to folder flexbuild_lsdk2108_github, and run the following command to get atf source code.

$ flex-builder -c atf -m ls1046ardb -b qspi

Go to atf source code folder components/firmware/atf/, please modify ddr controller initialization file plat/nxp/soc-ls1046a/ls1046ardb/ddr_init.c according to your custom board.

Rebuild atf with the following command.

$ flex-builder -c atf -m ls1046ardb -b qspi

You will get atf images bl2_qspi.pbl and fip_uboot.bin in folder flexbuild_lsdk2108_github/build/firmware/atf/ls1046ardb/.

Please deploy bl2_qspi.pbl at 0 and fip_uboot.bin at 0x100000 at QSPI flash.

[Johnson_s]

Thanks to you, the DDR initialization was successful. However, the third step was also necessary, so I will note it down.

3.In the ATF code, the erratum A09803 sets "ddr_out: address=0x1080114, value=0x401160", but in the DDRv tool-generated DDR initialization file, it was described as CCSR_BE_M(0x01080114, 0x00401150 | 0x00000020). Therefore, by modifying ddr_init.c to write 0x401170 to 0x114, it worked successfully.

Is this a bug?

[yipingwang]

Yes, please use the parameters provided in DDRv tool.