Can LS1046A EP raise legacy interrupt

[zy_mooncity]

Hi folks

I'm working with two LS1046A boards. One acts as  RC and the other acts as EP. I want to raise a legacy interrupt from EP to RC. Can it be possible? If yes, what's the configuration? Any reference code or appNote that I can resort to?

Thanks.

[ufedor]

Please refer to the QorIQ LS1046A Reference Manual, 25.5.1.13 PEX PFa PCIE message command register (PEX_PF0_MCR), 27 INTX:

"INTX: Assert/de-assert intx command. When sys_int goes from low to high, the core generates an Assert_INTx Message."

[zy_mooncity]

Thanks for the quick response.

I do notice this part. But it's unclear and insufficient for me. "When sys_int goes from low to high, the core generates an
Assert_INTx Message. When sys_int goes from high to low, the core generates a Deassert_INTx Message." Does it mean if INTX is set, sys_int will goes from low to high to generate an Assert_INTx Message?

From the program perspective, how to set up the legacy interrupt mechanism for the LS1046A EP?

In the EP end:

1. If I set bit 27 INTX to 1, a legacy interrupt will be generated to the LS1046A RC, right?

2. What's the interrupt vector for the software to handle? Is it the value set in the Interrupt_Line_Register?

In the RC end:

1. Which register should the LS1046A RC to read for the interrupt status?

2. How does the RC to de-assert the INTX?

[ufedor]

You wrote:

> In the EP end:

> 1. If I set bit 27 INTX to 1, a legacy interrupt will be generated to the LS1046A RC, right?

Correct.

> 2. What's the interrupt vector for the software to handle? Is it the value set in the Interrupt_Line_Register?

What do you mean?

> In the RC end:

> 1. Which register should the LS1046A RC to read for the interrupt status?

QorIQ LS1046A Reference Manual, 25.4.2.5 PCI Express Status Register (Status_Register)

> 2. How does the RC to de-assert the INTX?

RC does not possess a generic method for the EP INTx deassertion.

This is implementation dependent.

[zy_mooncity]

I mean the interrupt vector number to the GIC.

If the LS1046A EP assert a interrupt, it's should be a level interrupt because it's a PCI interrupt. It should be De-asserted once the LS1046A CPU (RC end ) handled the interrupt, or the interrupt is always active for the CPU to handle. The CPU should have a way to de-assert the interrupt, right? I'm wondered if the INTX bit is set by the LS1046A EP. How the CPU on the RC end to de-assert it.

[ufedor · Accepted solution]

You wrote:

>> In the EP end:

>> 2. What's the interrupt vector for the software to handle? Is it the value set in the Interrupt_Line_Register?

> I mean the interrupt vector number to the GIC.

Still not clear what does it mean for the EP.

> 2. How does the RC to de-assert the INTX?

RC does not possess a generic method for the EP INTx deassertion - i.e. it has to send a signal to the EP software (controlling the INTx assertion/deassertion) that its interrupt has been handled.

In which form the signal has to be sent is implementation dependent.

[zy_mooncity]

Thank you. I'll try on my target.

As for the interrupt vector. I mean once a legacy interrupt is raised by the EP, it will be routed to the GIC by the RC on the host. This is a interrupt vector number to map this legacy INTx.

[ufedor]

For the interrupt vector at the RC side refer to the QorIQ LS1046A Reference Manual, Table 5-1. Interrupt Assignments:

142 PEX1 INT (INTA, INTB, INTC or INTD)

152 PEX2 INT (INTA, INTB, INTC or INTD)

186 PEX3 INT (INTA, INTB, INTC or INTD)