BL2 DDR initialization issue with LS1012A

[cornetp]

Hello,

We went in troubles with DDR calibration on our custom board using LS1012A processor in TF-A boot mode. 

We noticed that the code of the mmdc_init method in BL2 is not exactly the same as the one in uBoot (used with PPA boot). It changes in the step "9a. calibrations now, wr lvl":

We had to apply the following patch to file atf/plat/nxp/drivers/ddr/fsl-mmdc/fsl_mmdc.c to fix our calibration issue:

--- fsl_mmdc.c.nok      2022-02-25 11:16:50.810313791 +0000
+++ fsl_mmdc.c.ok       2022-02-25 11:17:40.866313094 +0000
@@ -106,10 +106,13 @@
                                MPZQHWCTRL_ZQ_HW_FORCE);

        /* 9a. calibrations now, wr lvl */
-       out_be32(&mmdc->mdscr,  CMD_ADDR_LSB_MR_ADDR(0x84) | MDSCR_WL_EN |
+       out_be32(&mmdc->mdscr,  CMD_ADDR_LSB_MR_ADDR(0x84) |
                                MDSCR_ENABLE_CON_REQ |
                                CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1);

+       out_be32(&mmdc->mdscr,  MDSCR_ENABLE_CON_REQ | MDSCR_WL_EN |
+                               CMD_NORMAL);
+
        set_wait_for_bits_clear(&mmdc->mpwlgcr, MPWLGCR_HW_WL_EN,
                                MPWLGCR_HW_WL_EN);

Can you confirm that their is an issue with the code of mmdc_init in BL2 and that we are not doing something wrong? (we use yocto dunfell)

Thanks

[cornetp]

What do you advice? What is the corret way to do the WL calibration? Can you answer please?

[yipingwang]

From LSDK view, the current calibration code works correct for all NXP reference board including ls1012ardb/afrwy May I know the detailed information for the DIMM that used in your custom board? like size, brand. etc.

[cornetp]

We are using the MT41K512M16VRP-107 IT from Micron (1GB)

[cornetp]

I have printed the value of MPWLGCR  and MPWLDECTRL0 after WL calibration:

Old code (working correctly on our board)

• MPWLGCR = 0x10
• MPWLDECTRL0 = 0x001f0001

New code (after patch of 20 May 2019, not working on our board)

• MPWLGCR = 0x10
• MPWLDECTRL0 = 0x0012017f

Does it give you some clue? 

[yipingwang]

Please  refer to the update from the AE team.

We have checked all version local ls1012afwry boards that could be found, currently the LSDK code only tested with the ls1012afwry boards with two kinds of DDR, one is from Kingston, and the other one is from Micron, but is different from the one the customer used, (The FBGA code is D9SD0), it may be the possible reason for the issue.

If the old code is correct for the customer, then the customer could use the old code in their custom board, for this part, the only patch(20 May 2019) added to later SDK is targeted to fix the unstable issue found on ls1012afwry board during the system test.

[yipingwang]

Please refer to the following patch provided in yocto dunfell ATF source code.

From c8af318189df720a5e0e775410c1cc19d8ed4a1a Mon Sep 17 00:00:00 2001

From: Rajesh Bhagat <rajesh.bhagat@nxp.com>

Date: Mon, 20 May 2019 14:15:01 +0530

Subject: [PATCH] nxp: ddr: ls1012a: fixes random hang issue

Fixes random u-boot hang issue after DDR intialization

by changing programming sequence of hardware write-leveling

calibration.

Signed-off-by: Balkar Saini <balkar.saini@nxp.com>

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>

---

 plat/nxp/drivers/ddr/fsl-mmdc/fsl_mmdc.c | 5 +----

 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/plat/nxp/drivers/ddr/fsl-mmdc/fsl_mmdc.c b/plat/nxp/drivers/ddr/fsl-mmdc/fsl_mmdc.c

index 8efeddb47..e8f784597 100644

--- a/plat/nxp/drivers/ddr/fsl-mmdc/fsl_mmdc.c

+++ b/plat/nxp/drivers/ddr/fsl-mmdc/fsl_mmdc.c

@@ -106,13 +106,10 @@ void mmdc_init(const struct fsl_mmdc_info *priv)

                                MPZQHWCTRL_ZQ_HW_FORCE);

        /* 9a. calibrations now, wr lvl */

-       out_be32(&mmdc->mdscr,  CMD_ADDR_LSB_MR_ADDR(0x84) |

+       out_be32(&mmdc->mdscr,  CMD_ADDR_LSB_MR_ADDR(0x84) | MDSCR_WL_EN |

                                MDSCR_ENABLE_CON_REQ |

                                CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1);

-       out_be32(&mmdc->mdscr,  MDSCR_ENABLE_CON_REQ | MDSCR_WL_EN |

-                               CMD_NORMAL);

-

        set_wait_for_bits_clear(&mmdc->mpwlgcr, MPWLGCR_HW_WL_EN,

                                MPWLGCR_HW_WL_EN);

--

2.17.1

[cornetp]

Well this is annoying, because this specific patch from Rajesh Bhagat, causes the DDR initialization to fail on our custom board.

What do you advice? What is the corret way to do the WL calibration then?? Can we safely work with the "old" code?

[steina]

We are experiencing the exact same problem with W634GU6QB DDR RAM. Reverting this commit makes booting working again.