LS1012A integrates a hardware packet forwarding engine to provide high performance Ethernet interfaces. This document introduces PFE hardware and software decomposition and data flow, setting up two PFE Ethernet ports to implement Ethernet packets forwarding through PFE, how to modify PFE driver and dts file to set up single PFE Ethernet port on LS1012A custom boards. PFE hardware Structure PFE Software Decomposition and Data Flow Setting up Two PFE Ethernet Ports to Implement Ethernet Packets Forwarding Set up Single PFE Ethernet Port on LS1012A Custom Boards

Recently some customers are porting SDK 2.0 u-boot for LS1021ATWR to their custom boards. They intended to use GPIO lines to turn on/off LEDs for diagnostics and other various purposes. However GPIO driver is not supported in SDK 2.0 u-boot for LS102xa platform. The attached patch is used to add GPIO driver on LS1021ATWR platform based on SDK 2.0 u-boot code. Please use it in SDK 2.0 as the following: $ source ./fsl-setup-env -m ls1021atwr $ bitbake u-boot -c cleansstate $ bitbake u-boot -c patch Go to the folder build_ls1021atwr/tmp/work/ls1021atwr-fsl-linux-gnueabi/u-boot-qoriq/2016.01+fslgit-r0/git, apply the attached patch $ patch -p1<0001-ls1021xa-gpio.patch Go back to build_ls1021atwr folder to rebuild u-boot $ bitbake u-boot

DPDK(Data Plane Development Kit) provides a simple, complete framework for fast packet processing in data plane applications. This IPsec security gateway application demonstrates the implementation of a security gateway using DPDK cryptodev framework with crypto protocol offloading support. This document introduces DPDK IPsec gateway application architecture, DPAA2 SEC driver and ipsec-secgw application implementation for crypto protocol offloading, running ipsec-secgw application on LS2088ARDB.

IEEE Std 1588 standard is for a precision clock synchronization protocol for networked measurement and control, define a Precision Time Protocol (PTP) designed to synchronize real-time clocks in a distributed system. This document introduces IEEE 1588 related basic concept and Precision Time Protocol, hardware assist for 1588 compliant time stamping on QorIQ  LS1021 platform, Linux Kernel PTP framework device driver implementation working with ptpd stack, IEEE 1588 test setup on LS1021ATSN platform and results. IEEE 1588 Introduction and Precision Time Protocol Hardware Assist for 1588 Compliant Time Stamping on QorIQ LS1021 Platform      2.1 Accessing Timer Registers      2.2. Time-Stamping on Ethernet Frame Reception for eTSEC      2.3. Time-Stamping on Ethernet Frame Transmission for eTSEC IEEE 1588 PTP Linux Device Driver and PTPd Application     3.1 IEEE 1588 Linux Software Structure     3.2 IEEE 1588 Linux Device Driver 3.3 PTPd Application Setup IEEE 1588 test on LS1021ATSN Platform    4.1 Build Images with OpenIL    4.2 Setup IEEE 1588 test environment on LS1021ATSN    4.3 Test result

The Layerscape LS1028A industrial applications processor includes a TSN-enabled Ethernet switch and Ethernet controllers to support converged IT and OT networks. Two powerful 64-bit ARM v8 cores support real-time processing for industrial control, as well as virtual machines for edge computing in the IoT. The integrated GPU and LCD controller enable Human Machine Interface (HMI) systems with next-generation interfaces. Integrated Trust Architecture with crytographic offload provide a trusted platform with encrypted communications for secure applications and services. Product Page Reference Design KEY ELEMENTS Dual 64-bit ARM v8 processors for real-time processing Full virtualization support for IoT edge computing TSN-enabled switch for industrial TSN bridge applications TSN-enabled Ethernet controllers for TSN endpoint applications Support Human Machine Interface applications with integrated GPU and LCD controller Trust architecture provides root of trust as a basis for trusted applications and services The LS1028A will be a part of the NXP 15-year product longevity program TARGET APPLICATIONS Factory Automation Process Automation Programmable Logic Controller Motion Controller Industrial IoT gateway Human Machine Interface (HMI)

Getting RCW image: Getting UEFI image:                              Getting PPA image: Getting Linux kernel and DTB, and Root FS images: - Download Image , fsl-ls1043a-uefi-rdb.dtb and fsl-image-core-ls1043ardb.ext2.gz . - Copy Image and fsl-image-core-ls1043ardb.ext2.gz to the TFTP server directory. Getting GRUB2 image for AARCH64 and sample GRUB configuration: - Download grub image from this location. - Download sample grub configuration from here . Placing GRUB image on FAT formatted SD card: Install FAT32 file system on SD card - Use the DISKPART utililty on windows command prompt to format a SD card with FAT32 file system. Use the following snapshot for reference - Copy grubaa64.efi and ls1043a-grub.cfg to the SD card. Booting to UEFI prompt on LS1043a RDB Board: Boot to u-boot prompt from NOR flash bank 0 on LS1043a RDB.  Setup serial port connection on host machine, to capture logs from the target LS1043a RDB board.. Reset the board to boot u-boot on bank 0, assuming that there is a valid u-boot image flashed on the primary bank 0. Copy Images to NOR flash alternate bank using u-boot commands sete uefi 'tftp 80000000 LS1043ARDB_EFI.fd; erase 0x64400000 0x644FFFFF ; cp.b 80000000 0x64400000 $filesize' sete rcw 'tftp 80000000 rcw_uefi_1500.bin; erase 0x64000000 0x640FFFFF ; cp.b 80000000 0x64000000 $filesize' sete ppa 'tftp 80000000 ppa.itb; erase 0x64500000 0x645FFFFF ; cp.b 80000000 0x64500000 $filesize' sete dtb 'tftp 80000000 fsl-ls1043a-uefi-rdb.dtb; erase 0x65B00000 0x65BFFFFF; cp.b 80000000 65B00000 $filesize' run uefi run ppa run rcw run dtb Note: The host machine is assumed to be having tftp server running, with the relevant files in place. The rcw, uefi, dtb and ppa images can also be found at compass link shared above. Note: Make sure SD card is inserted into the SD card slot on the board. Reset RDB to boot from NOR flash bank 4 => cpld reset altbank You should get UEFI boot prompt, as shown in the image below. Enter 2 to load Shell. On the Shell prompt run the following commands Shell> FS0:   Shell> ls You should see a list of the grub executable and configurations files present on SD card. Booting Linux via PXE on LS1043a RDB: Note: atftpd or tftpd-hpa, is required as tftp server for PXE boot to work. tftpd is not supported.  Load grub by entering the name of the grub executable. Shell> grubaa64.efi On the grub prompt, setup the server and client IPs for TFTP transfer. grub> set net_default_server=<server_ip> grub> net_add_addr eno0 efinet0 <client_ip> Load the grub configuration. grub> configfile (hd3,msdos1)/ls1043a-grub.cfg Grub menu is listed. Choose the entry for liinux boot. See the snapshot below for reference. Linux boot should start in around 7-8 minutes. Data transfer speed is around 100 KB/s.

OpenWrt is a highly extensible GNU/Linux distribution for embedded devices (typically wireless routers), OpenWrt is built from the ground up to be a full-featured, easily modifiable operating system for your router. LEDE is based on OpenWrt, targeting a wide range of wireless SOHO routers and non-network device. This document introduces how to porting and running OpenWrt/LEDE on QorIQ LS1012/LS1043 platform. 1. Porting OpenWrt/LEDE Source on QorIQ Layerscape Platforms 2. Deploy OpenWrt/LEDE Images to Boot up the System 3. Verify VLAN Interface and PFE in LEDE System

This document introduces porting TDM Linux driver working in internal loopback mode to do verification during custom boards bringing up and verification stage. 1. TDM Interface Configuration to Support Internal Loopback Mode 2. Modify Linux Kernel Driver to Make TDM Working in Internal Loopback Mode 3. Build TDM Driver into Linux Kernel and do verification on the target board

The integrated flash controller (IFC) is used to interface with external asynchronous/synchronous NAND flash, asynchronous NOR flash, SRAM, generic ASIC memory and EPROM. This document introduces how to configure IFC controller on QorIQ LS, T and P series custom boards, uses LS1043 custom board integrating NAND Flash MT29F64G08CBCBBH1 as an example to demonstrate IFC flash timing parameters calculation and control registers configuration, CodeWarrior initialization file customization and u-boot source code porting. 1. IFC Memory Mapped Registers Introduction 2. Calculate IFC Flash Timing Values and Configure Control Registers 3. Customize CodeWarrior Initialization File with the Calculated IFC Timing 4. Porting U-BOOT Source with the Calculated IFC Timing

This document introduces a method to separate control plane and data plane between GPP(ARM) and AIOP based on different L4 protocols implemented in the AIOP software. So far, in the current MC version, this scenario could not be implemented from WRIOP using DPDMUX, so it is a good choice for users to separate the traffic in AIOP.   1. Basic Concept of DPAA2 Objects   2. AIOP Application to Implement Control in ARM and Data Plane in AIOP   3. Build AIOP Application Project with CodeWarrior   4. Running AIOP Application Program on LS2085ARDB

The u-boot in SDK2.0 has a bug on SGMII2.5 support. Need to add the patch.

This document introduces how to configure RCW to support GPIO on LS1043 platform, how to configure Linux Kernel to load Linux GPIO driver to access GPIO from SYSFS and using loopback method to do verification on the target board. RCW configuration to support GPIO Configure GPIO driver in Linux Kernel Verify GPIO on the target board

This file shows up LS1024A GMAC2 debug, no software support in barebox only workable in kernel. and If using RTL Phy need to add TX_CLK and RX_CLK delay.

This Documentation shows how to make a mass production NAND Flash image for QorIQ IFC NAND flash interface by external NAND Flash programmer.

The attached patch is to support Aquantia AQR107 in LS1043A.

The attached patch is to support DDR3L in LS1043A. The SDK version is Linux-LS1043A-SDK-V0.5-SOURCE-20151223-yocto.iso. Not SDK2.0. The DDR3L part number is two Winbond W632GU6KB(16M x 8 banks x 16 bits DDR3L SDRAM).

On LS2085 platform, the basic networking product performs autonomous IP forwarding and IPSEC on the AIOP, data path functions run mostly independent of the GPP software and only involve GPP when necessary. NADK(Network Acceleration Development Kit) is a complete user space development kit for networking applications. This IPSEC application is implemented in Linux user space using NADK framework, this application learns the Linux configuration through the netlink event notification and sends the configuration to AIOP DP using the respective NF APIs. The application invokes NF APIs to send configuration details to IPsec data path on the AIOP. 1. Overview and Architecture of the AIOP-NADK Based IPSEC Application 2. NADK Based GPP Listener Program Design 2.1 NADK APIs Introduction Used in the Application 2.2 Packet Processing in Multiple Threads Mode NADK Application 2.3 IPSEC XFRM Events monitored by the Listener 3. IPSEC Application communicates with AIOP through NF APIs 3.1 IPSEC provided features implemented at AIOP 3.2 IPSEC NF APIs Used to Configure AIOP 3.3 The process of add SPD policy in the IPSEC Application 4. Setup Networking Environment to Verify the IPSEC application

1. Bootflow Overview of LS2 2. U-BOOT Workflow for LS2085 3. LS2085QDS configuration and Initialization in U-BOOT

Currently rate limiting is supported on TX side only via IOCTL call FM_PORT_IOC_SET_RATE_LIMIT. A user-space application has to be implement which opens the character driver interface of the TX port and issue the IOCTL. The rate_limit structure (mentioned below) has to be filled to implement the restriction.   For example:   fd = open ("/dev/fm0_port_tx5", O_RDWR);   err = ioctl(fd, FM_PORT_IOC_SET_RATE_LIMIT, &fm_port);   Structure to pass to the IOCTL: /**************************************************************************//** @Description@@   A structure for defining Tx rate limiting (Must match struct t_FmPortRateLimit defined in fm_port_ext.h) *//***************************************************************************/ typedef struct ioc_fm_port_rate_limit_t { uint16_t max_burst_size;         /**< in KBytes for Tx ports, in frames for offline parsing ports. (note that for early chips burst size is rounded up to a multiply of 1000 frames).*/     uint32_t rate_limit; /**< in Kb/sec for Tx ports, in frame/sec for offline parsing ports. Rate limit refers to data rate (rather than line rate). */ ioc_fm_port_dual_rate_limiter_scale_down rate_limit_divider; /**< For offline parsing ports only. Not-valid for some earlier chip revisions */ } ioc_fm_port_rate_limit_t; Further information in the below link. http://www.freescale.com/infocenter/index.jsp?topic=%2FQORIQSDK%2F2283674.html