Content originally posted in LPCWare by Ex-Zero on Tue Nov 15 14:06:06 MST 2011
That's your clock divider CLKDIV, see user manual:
Quote:
20.5.1 A/D Control Register (AD0CR - 0x4001 C000)
15:8 CLKDIV The APB clock (PCLK) is divided by CLKDIV +1 to produce the clock for the ADC, which
should be less than or equal to 4.5 MHz. Typically, software should program the smallest
value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such
as a high-impedance analog source) a slower clock may be desirable.
Your sampling frequency depends on something like ADCRead(i), where you can find the start of conversion :)
If you want to use a fixed frequency you can use 'Optional conversion on transition on input pin or Timer Match signal' :eek:
User manual:
Quote:
Table 268. A/D Control Register (AD0CR - address 0x4001 C000) bit description
26:24 START When the BURST bit is 0, these bits control whether and when an A/D conversion is
started:
0
0x0 No start (this value should be used when clearing PDN to 0).
0x1 Start conversion now.
[COLOR=Red]0x2 Start conversion when the edge selected by bit 27 occurs on
PIO0_2/SSEL/CT16B0_CAP0.
0x3 Start conversion when the edge selected by bit 27 occurs on
PIO1_5/DIR/CT32B0_CAP0.
0x4 Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT0[1].
0x5 Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT1[1].
0x6 Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT0[1].
0x7 Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT1[1].[/COLOR]
