What Speed External Static RAM

[lpcware]

Content originally posted in LPCWare by MikeSimmonds on Thu Mar 08 06:44:17 MST 2012
Hi.

Using LPC1778, want to add external static RAM.

If I run CPU at, say 80-100 MHz, what speed grade RAM chips do I need
for zero wait states (if possible) or what wait states will I have to use.

What effect of throughput will this have (how can I calculate/estimate) when I do a lot of read/write to external RAM?

I'll be using 2x16 bit wide devices on a 32 bit data bus?

Cheers, Mike

[lpcware]

Content originally posted in LPCWare by Rob65 on Thu Mar 08 12:57:28 MST 2012

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Quote: MikeSimmonds
Mr Rob

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Mr ... makes me feel old but I'm only from the year 7AD, not 7 A.D. :D

Of course you'll have to place the SRAM timings on-top of the LPC177x timings. If you want high throughput numbers you don't want the access time of the SRAM to slow you down too much. Remember that a delay that is just one ns too long (e.g. address stable until data valid) means that you have to add a full wait state (of 12.5 ns) which might mean you go from 37.5 ns cycle time to 50 ns.

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Quote:

Again thanks.

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Glad to be of help. I used to read those specs on a daily basis and to be honest - the fact that I noticed the <TBD> fields more or less triggered me to trigger NXP. So actually the objective spec made me answer this sooner than I otherwise might have ;)

Regards,
[INDENT]Rob
[/INDENT]

[lpcware]

Content originally posted in LPCWare by MikeSimmonds on Thu Mar 08 12:38:16 MST 2012
Mr Rob, thank you so much for your lucid clarifications; and I take on board your comments about documentation nomenclature. [I am indeed a firmware programmer first and foremost.]

Obviously, I will not take your numbers without doing my own calculations, but is does appear that I can save a bit of money with the design as I asked for 12ns memory parts -- but it seems that that would be wasted and 20ns or so will do.

Again thanks.
Mike

[lpcware]

Content originally posted in LPCWare by Rob65 on Thu Mar 08 12:24:14 MST 2012

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Quote: MikeSimmonds
I was reading the "User Manual" which is what I (and most other companies) would call the data sheet. Not the so-called overview document which I and others would term a summary.

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I beg to differ.

The datasheet contains information with detailed electrical information: voltage levels, timing and some more electrical specifications (like ADC linearity) while the user manual contains mostly what programmers want/need to know to use the device.

You need what is written in the datasheet in order to be able to create a hardware design. You need what is written in the user manual in order to be able to create the software.
I am using the user manual on a (almost) daily basis, the datasheet I only needed to finish my hardware design.

Of course there is always the overlap: for the EMC you'll need both documents since you are concerned about programming the hardware timing.

You will see similar constructions with the real 'biggies'  like Intel, IBM, Motorola and ARM; they all have a separate 'programmers' manual with a description of device registers and its use.

Oh ... if you are going really deep down (for some of us this looks deeper than for others...) you might also need the manuals from ARM describing the ARM Cortex M3 architecture and the instruction set but as long as you are not going to work on very low level startup code, your own multitasking scheduler or need detailed information on interrupt timing you will get by without those docs.

Rob

[lpcware]

Content originally posted in LPCWare by Rob65 on Thu Mar 08 12:12:26 MST 2012
Indeed,

I've looked at the EMC in a little bit more detail myself.
There is a general picture (figure 16) showing the read and write timings but I do admit it is not the easiest picture to read. But then, this captures what some of the 'biggies'  need 3 or 4 pictures for :rolleyes:

Actually, there are 3 pictures ... figure 17 shows the read/write access when PB=1 and figure 18 shows a burst read cycle.

PB is an internal signal that defines the type of SRAM that is used. With PB=0 you capture the byte wide memory chips being used. Here the BLS0..3 signals are used as write enable. PB=1 is used for word wide memory that uses both a WE and a BLS (Byte Lane Select) signal.

Let's stay with figure 16 (byte wide memory): RD1 is the time from CS low to Address stable. RD5 is ... ehh... used 3 times in the diagram - since this is read timing this means the data should be valid at least RD5 after the latest event (CS low, OE low, address stable) occurs. From the picture, OE could be low before CS and the address couldbe stable before OE low so that explains where this strange timing comes from.

RD1 is fixed max 2.5 ns. RD5 is programmable (programmable wait states) bu the lowest (max) value is 2*12.5 - 7.2 = 17.8 ns (WAITRD = 1..32, WAITOEN=0..)
Most likely the limiting time is defined by RD2 + RD4 + RD7.
With the max values (with lowest delays programmed) being: 2.5 + (2*12.5-1) + <tbd> = 26.5 + <tbd> ns.

We actually would need NXP's knowledge here but I am guessing (I did not read the complete spec & user manual) that all memory accesses are clocked by Tcy. I am also guessing that RD7 is some very low value.
With RD2+RD4 being more than 2 and less than 3 Tcy cycles I am guessing that the highest achievable speed is at  37.5 ns. For a burst read this could be 25 ns.

The <tbd> in the datasheet worries me only a little bit, these timings may look critical but when you look at the pictures in more detail you'll notice that those are not the critical timings that should be of concern.
Still ... it is not nice to see those and the datasheet is marked as "Objective data sheet" meaning that this is not the final product data sheet.

I'm hoping that NXP can clear these TBD items - and maybe even give still more detail.

Regards,
[INDENT]Rob
[/INDENT]

[lpcware]

Content originally posted in LPCWare by MikeSimmonds on Thu Mar 08 11:53:13 MST 2012
Apologies.

I was reading the "User Manual" which is what I (and most other companies) would call the data sheet. Not the so-called overview document which I and others would term a summary.

Still ...

This gives me something new to read.

Ta for the pointer.

[lpcware]

Content originally posted in LPCWare by MikeSimmonds on Thu Mar 08 11:25:44 MST 2012
Thanks for the reply.
I have read the data sheet, but I am unsure what 'numbers' to use.

NXP don't seem to give read/write waveform diagrams like Atmel and the other biggies.

So I don't have info on what part (i.e. how long) of the bus cycle the RAM's data must be valid. And how many cpu cycles is a bus cycle (if not 1) anyway. What do wait state cycles look like.

I'll plough back into the text to see if the info is there -- but diagrams are so much clearer!

Mike

[lpcware]

Content originally posted in LPCWare by Rob65 on Thu Mar 08 10:18:22 MST 2012
You might want to check out the lpc177x/178x datasheet available here.
In section 11.2 you'll find a nice overview of all the timing characteristics.

You will also need to look for the user manual and check on the programming of the External Memory Controller.

I understand this may seem an easy solution to your question and not the answer you are waiting for (and yes - it is) but in the end you will have to figure out how to connect and program the EMC and that is just too specific to just answer in a few lines in the forum.

I have been using different controllers with SRAM and with SDRAM - configuring the whole thing can be tricky and I don't have a ready to go example for the lpc177x.

This is something I would almost except to be covered in an Application Note but I was unable to find one in the lpc1778 support docs.

Maybe someone else can help you out with an example - even if not a ready to go one, I know from my own experience that any example is helpful.
Otherwise, start reading and prepare to have more detailed questions we maybe could answer.

Regards,

Rob