PWM question (how to avoid glitches?)

[lpcware]

Content originally posted in LPCWare by simonbr on Mon Apr 19 02:59:13 MST 2010
Hi,

In the ECCP module in Microchip processors, the contents of the pulse width register (CCPR) are transferred to the actual "match register" at timer reset. See for example fig. 11-3 on page 149 in http://ww1.microchip.com/downloads/en/DeviceDoc/41303G.pdf
So you can change the pulse width value at any time, and in the next cycle the correct pulse width value will be used.

I wonder if there are similar buffers for the match registers of the LPC1343. If there are, it is not apparent from the user guide (see chapter 15). And if the match registers are [I]not[/I] buffered, then how do I avoid glitches when varying the pulse width?

For example, suppose a period of 1000, a current PWM match value of 505, and I happen to write a new match value of 495 at the moment that the timer has advanced to 500. Then for that whole cycle the PWM output would stay low (as the timer is already past the new match value)?

Best regards,
Simon Brouwer

[lpcware]

Content originally posted in LPCWare by simonbr on Wed Apr 21 01:01:32 MST 2010

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Quote: micrio
Another suggestion is to take an interrupt on match and update the match register at that time.

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I thought about that, and the best way would be to get the interrupt right after the PWM match occurs.
However this would not work reliably in all cases. Suppose a period of 1000, a PWM match value of 999, and a new PWM match value of 1. If the timer runs at maximum speed the interrupt handler is not able to set the new match value before the timer is already past it.

Anyway, so far the most important question has not been answered. Did the writers of the LPC13xx manual think it unnecessary to mention it, or did the designers of the chip think it unnecessary to implement it?
If the PWM match registers are actually buffered, none of the suggested workarounds would be necessary.

I think I need to do an experiment to find out.

[lpcware]

Content originally posted in LPCWare by micrio on Tue Apr 20 10:36:39 MST 2010
Another suggestion is to take an interrupt on match and update the match register at that time.

[lpcware]

Content originally posted in LPCWare by simonbr on Tue Apr 20 07:39:59 MST 2010

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Quote: jmg
It would be a strange PWM design that did not buffer!!.

Look at both the User Manual, and Data sheets

http://www.nxp.com/documents/user_manual/UM10375.pdf
http://ics.nxp.com/products/lpc1000/datasheet/lpc1311.lpc1313.lpc1342.lpc1343.pdf

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Of course I already did before posting this question.

Can [I]you[/I] find any suggestion in those documents that the PWM match registers are buffered?

[lpcware]

Content originally posted in LPCWare by jmg on Mon Apr 19 20:23:35 MST 2010
It would be a strange PWM design that did not buffer!!.

Look at both the User Manual, and Data sheets

http://www.nxp.com/documents/user_manual/UM10375.pdf
http://ics.nxp.com/products/lpc1000/datasheet/lpc1311.lpc1313.lpc1342.lpc1343.pdf

[lpcware]

Content originally posted in LPCWare by micrio on Mon Apr 19 20:20:47 MST 2010
There is a kluge that you can implement to solve your problem. Since the CPU and counters run off the same clock, they are synchronous, you can determine a safe count range when it is OK to change the match register.

For example suppose the match register is currently 500 and you want to change it to 450. You would read the counter and if the value were from 10 to 400 then it would be safe to change the value. Otherwise you would spin until it came into the safe range. The safe range would have to be determined experimentally. You would probably have to disable interrupts between the time you read the counter and when you write the match register.