Wait state adjustments

[lpcware]

Content originally posted in LPCWare by Brinkand on Wed Sep 22 01:31:54 MST 2010
I am using an LPC1311, which I am clocking down to 48MHz. I recall that there should be 3 wait states et 72MHz, but I cannot find the information anywhere.

Please help me find:

Information on wait states?

How do I reduce the wait states?

[lpcware]

Content originally posted in LPCWare by ataru on Wed Dec 01 08:42:36 MST 2010
Any reason the flashcfg register is not included in this header file, at least as far as I can tell ?

[lpcware]

Content originally posted in LPCWare by domen on Mon Nov 08 02:24:21 MST 2010
It's not that simple.

Flash transfers go through ICode bus... wait states are for that bus, they don't necessary stall the CPU. Also, yes, 32-bit fetches mean 2 thumb instructions can be fetched at once. And then there's 64-bit cache.

To sum it up: Flash interface on cortex-m3 is quite smart. IIRC you don't even get speed increases when running code from RAM.

Or you could just benchmark it, to see it really makes a difference.

[lpcware]

Content originally posted in LPCWare by cyberstudio on Sat Nov 06 15:19:49 MST 2010
It appears that by default, it is 3 wait states. How wide is the flash memory bus? (The average instruction is 16-bits wide so for example will it read 2 instructions at a time?)

If not, then what is the point of setting the system clock frequency higher? 1 wait state at 20MHz and 2 wait states at 40MHz is going to be the same speed (e.g. as in LPC11xx) and 3 wait states at 50MHz will end up actually being slower.

[lpcware]

Content originally posted in LPCWare by Brinkand on Wed Sep 22 05:03:21 MST 2010
Thank You very much.

[lpcware]

Content originally posted in LPCWare by domen on Wed Sep 22 02:34:14 MST 2010
User's manual, Flash memory access, FLASHCFG register.