SSP interrupt needed for SPI?

[lpcware]

Content originally posted in LPCWare by kjhuebner on Wed Nov 17 09:26:52 MST 2010
Does the LPC1114 chip require that I establish a SSP interrupt?  The examples I've seen do this in the code:

[SIZE=2][COLOR=#3f7f5f][SIZE=2][COLOR=#3f7f5f][LEFT]NVIC_EnableIRQ(SSP0_IRQn);[/LEFT]
[/COLOR][/SIZE][/COLOR][/SIZE][SIZE=2][LEFT][/LEFT]
[/SIZE][SIZE=2][COLOR=#3f7f5f][SIZE=2][COLOR=#3f7f5f][LEFT]
// Set SSPINMS registers to enable interrupts
// enable all error related interrupts
SSP_SSP0IMSC = ( SSP_SSP0IMSC_RORIM_ENBL // Enable overrun interrupt[/LEFT]
| SSP_SSP0IMSC_RTIM_ENBL); // Enable timeout interrupt
[/COLOR][/SIZE][/COLOR][/SIZE]
I would like to do SPI communication solely by polling without an active SSP interrupt.  My fear is the SSP interrupt will interfere with my other interrupts.

If someone could point me to some source code that does SPI without the SSP interrupt, I would be most appreciative.:)

Thanks,
Ken

[lpcware]

Content originally posted in LPCWare by cyberstudio on Wed Nov 17 11:24:30 MST 2010
In fact, the SSP interrupt is rather useless in my opinion. It waits 32 clocks, or a half full FIFO, before interrupting. You may poll some status register to know exactly if SSP is busy, whether the transmit and receive FIFOs are empty or full, etc.