SPI debugging

[lpcware]

Content originally posted in LPCWare by drat on Wed Aug 24 19:36:53 MST 2011
Hi,

I am developing SPI on the LPC17xx and I was wondering if the SSEL needs to be controlled by me or will the hardware do that?

the setup code is as follows:

SCB_PCLKSEL0 |= (1<<16);//PERIPHERAL CLOCK SELECTION FOR SPI
PCB_PINSEL0 |= (3<<30);  //select SCK on pin P0.15
PCB_PINSEL1 |= 0b111111;  //select SSEL -> P0.16 and MISO -> P0.17 and MOSI -> P0.18
S0SPCCR |= 8;//CLOCK DEVIDER
S0SPCR |= (1<<3);//CPHA = 1; DATA IS SAMPLED ON THE SECOND CLOCK EDGE OF SCK
S0SPCR |= (1<<4);//CPOL = 1; CLOCK POLARITY; ACTIVE LOW
S0SPCR |= (1<<5);//MSTR = 1; MASTER MODE;

can anybody help me understand why SPI does not work?

[lpcware]

Content originally posted in LPCWare by drat on Thu Aug 25 19:20:53 MST 2011
Thanks everybody for your kind help!

I realized that the SPI line was running faster than I thought and therefore I was not scoping it right. :o

yet again thanks for all your help guys!

[lpcware]

Content originally posted in LPCWare by NXP_Europe on Thu Aug 25 14:48:03 MST 2011
Hello drat,

For some general info about the SPI-bus

see ...
http://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus

[lpcware]

Content originally posted in LPCWare by Ex-Zero on Thu Aug 25 14:09:16 MST 2011

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Quote: drat
My problem is when i scope the pins i do not see a clock signal or a data out signal

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#1 Are you aware that SPI means shifting bits from MOSI to slave and back to MISO ? Without writing data to your SPI data register you will see nothing :eek:

#2 Perhaps it's a good idea to use SSP instead of SPI (see sample above).

#3 Also it could be a good idea to zip and post your project :)

#4 Did you check PCSPI bit in PCONP ?

[lpcware]

Content originally posted in LPCWare by drat on Thu Aug 25 13:37:20 MST 2011
Thanks Zero and rob.

My problem is when i scope the pins i do not see a clock signal or a data out signal.

the pins are configured to having internal pull ups and i was wondering if i have set up some thing wrong. also I have changed the P0.16 from being hardware controlled to being controlled by me i.e it is in gpio configuration. when i scope p0.16 i can see it jump up and down but the other pins seem like they are dead.

any thoughts?

[lpcware]

Content originally posted in LPCWare by Rob65 on Thu Aug 25 00:25:58 MST 2011
Drat,

SSEL can be controlled by the SSP module but then it works as stated in the user manual. Then for each and every frame (byte/word) that you send, the SSEL becomes active and inactive in between.

Why? Cause this is the 'SPI standard' although I don't know why because the SPI devices I know all have a 'chip select' that is active during a whole transaction of multiple words.

So for most of your application you are free to use any GPIO pin as SSEL/CS since that is how you want to use it.

Regards,
[INDENT]Rob
[/INDENT]

[lpcware]

Content originally posted in LPCWare by Ex-Zero on Wed Aug 24 19:55:50 MST 2011
There's an SSP sample in examples in NXP_LPCXpresso1769_MCB1700_2011-02-11.zip.

It's SSP0Init could help you:

void SSP0Init( void )
{
  uint8_t i, Dummy=Dummy;

  /* Enable AHB clock to the SSP0. */
  LPC_SC->PCONP |= (0x1<<21);

  /* Further divider is needed on SSP0 clock. Using default divided by 4 */
  LPC_SC->PCLKSEL1 &= ~(0x3<<10);

  /* P0.15~0.18 as SSP0 */
  LPC_PINCON->PINSEL0 &= ~(0x3UL<<30);
  LPC_PINCON->PINSEL0 |= (0x2UL<<30);
  LPC_PINCON->PINSEL1 &= ~((0x3<<0)|(0x3<<2)|(0x3<<4));
  LPC_PINCON->PINSEL1 |= ((0x2<<0)|(0x2<<2)|(0x2<<4));
  
#if !USE_CS
  LPC_PINCON->PINSEL1 &= ~(0x3<<0);
  LPC_GPIO0->FIODIR |= (0x1<<16);        /* P0.16 defined as GPIO and Outputs */
#endif
        
  /* Set DSS data to 8-bit, Frame format SPI, CPOL = 0, CPHA = 0, and SCR is 15 */
  LPC_SSP0->CR0 = 0x0707;

  /* SSPCPSR clock prescale register, master mode, minimum divisor is 0x02 */
  LPC_SSP0->CPSR = 0x2;

  for ( i = 0; i < FIFOSIZE; i++ )
  {
    Dummy = LPC_SSP0->DR;        /* clear the RxFIFO */
  }

  /* Enable the SSP Interrupt */
  NVIC_EnableIRQ(SSP0_IRQn);
    
  /* Device select as master, SSP Enabled */
#if LOOPBACK_MODE
  LPC_SSP0->CR1 = SSPCR1_LBM | SSPCR1_SSE;
#else
#if SSP_SLAVE
  /* Slave mode */
  if ( LPC_SSP0->CR1 & SSPCR1_SSE )
  {
    /* The slave bit can't be set until SSE bit is zero. */
    LPC_SSP0->CR1 &= ~SSPCR1_SSE;
  }
  LPC_SSP0->CR1 = SSPCR1_MS;        /* Enable slave bit first */
  LPC_SSP0->CR1 |= SSPCR1_SSE;    /* Enable SSP */
#else
  /* Master mode */
  LPC_SSP0->CR1 = SSPCR1_SSE;
#endif
#endif
  /* Set SSPINMS registers to enable interrupts */
  /* enable all error related interrupts */
  LPC_SSP0->IMSC = SSPIMSC_RORIM | SSPIMSC_RTIM;
  return;
}

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Quote:

...SSEL needs to be controlled by me or will the hardware do that?

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As shown in this sample you can control CS yourself (with GPIO) or let the hardware do that