LPC1778 Internal EEPROM

[lpcware]

Content originally posted in LPCWare by MikeSimmonds on Fri Apr 20 01:00:54 MST 2012
[FONT=Tahoma][SIZE=2]The NXP user manual UM10470 is distressing ambibuous and does not go to a sufficient level of detail to permit coding for the internal EEPROM!

(And the 176x variants do not have this feature.)

Can anyone supply example code (preferably in assembler, but straight "C" will do)?

By the way NXP, why do you have ABSOLUTELY NO examples for the LPC177x/178x (apart from the CMSIS libs)? *** [SIZE=3][B]SHAME ON YOU[/B][SIZE=2] ***[/SIZE][/SIZE]

The MCUs are sufficiently different that you were forced to supply a different CMSIS for 177x and 178x from the 176x (which you very confusingly name as 17xx -- even though this excludes 177x and 178x).

Thanks in advance to [I]anyone[/I] who can help out.

Cheers, Mike
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[lpcware]

Content originally posted in LPCWare by NXP_USA on Mon Apr 23 15:28:35 MST 2012

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Quote: MikeSimmonds
[FONT=Tahoma][SIZE=2]...
So, NXP support,
How long does write to page buffer take (in clock cycles would do)?
I.e. can I load up a complete page buffer without long delays (wait states)?
Same for read: will read of the entire array have unacceptable 'wait states'?

Wear level info:
If I repeatedly have to update a single byte on a page, does this affect the erase/write cycle count for other data on the same page?
...
Cheers, Mike
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Hello, here is some more information. Multiple writes to a page do not affect the cycle count, but multiple erases do. This means that if you have to update a single byte repeatedly, it will affect the page cycle count since the whole page (64 bytes) must be erased to rewrite that one byte. It takes a total of 5.3 ms maximum for an erase/program operation (64 bytes) on the EEPROM to complete when the EEPROM is operating at 200 kHz. We recommend a typical frequency of 375 kHz so the erase/program time should be much less. Read and writes to the EEPROM registers (through which you can access the EEPROM) should occur with zero wait states. We are updating the datasheet soon to include the EEPROM timing information.

-NXP

[lpcware]

Content originally posted in LPCWare by kendwyer on Mon Apr 23 15:26:23 MST 2012
The is an EEPROM example here:
http://sw.lpcware.com/?p=lpc177x_8x.git&a=tree

[lpcware]

Content originally posted in LPCWare by MikeSimmonds on Mon Apr 23 10:35:29 MST 2012
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Quote: researchinnovation

Yesterday you got the code for your application on website..Rite?
Is it working now...?

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I'll be sure to let you know in 6 to 8 weeks when the other part of the team produces a prototype board for me to use. :)
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[lpcware]

Content originally posted in LPCWare by researchinnovation on Fri Apr 20 22:21:54 MST 2012
@MikeSimmonds...
Hi...!!
Yesterday you got the code for your application on website..Rite?
Is it working now...?


Thanks &  Regards....:)

[lpcware]

Content originally posted in LPCWare by MikeSimmonds on Fri Apr 20 09:52:49 MST 2012

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Quote: MikeSimmonds
[FONT=Tahoma][SIZE=2]
So, NXP support,
How long does write to page buffer take (in clock cycles would do)?
I.e. can I load up a complete page buffer without long delays (wait states)?
Same for read: will read of the entire array have unacceptable 'wait states'?

Wear level info:
If I repeatedly have to update a single byte on a page, does this affect the erase/write cycle count for other data on the same page?[/SIZE][/FONT]

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[FONT=Tahoma][SIZE=2]
Anyone from NXP reading this thread?

Mike
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[lpcware]

Content originally posted in LPCWare by MikeSimmonds on Fri Apr 20 03:51:15 MST 2012
[FONT=Tahoma][SIZE=2]Appologies (with some reservations) to NXP. :o

I found "LPC177x_8x.PDL.110602 (v.2.0)" on the [I]documentation[/I] page for the LPC1778 page on the NXP site (http://www.nxp.com/products/microcontrollers/cortex_m3/lpc1700).

This has a very simple and restricted example for the eeprom.
But still leaves unanswered issues:

So, NXP support,
How long does write to page buffer take (in clock cycles would do)?
I.e. can I load up a complete page buffer without long delays (wait states)?
Same for read: will read of the entire array have unacceptable 'wait states'?

Wear level info:
If I repeatedly have to update a single byte on a page, does this affect the erase/write cycle count for other data on the same page?

@The FallGuy, thanks for the hint, but I found (stummbled on) it by myself.

To CodeRed, why (oh why oh why) did you not include this in the LPCXpresso
Examples; all you supply is the CMSIS libs for LPC177x/178x.
That would have saved a lot of hassle.
After all, your product is not just for LPCXpresso boards.

Strong NFS to include this in your next release.

Cheers, Mike
[/SIZE][/FONT]

[lpcware]

Content originally posted in LPCWare by TheFallGuy on Fri Apr 20 03:10:40 MST 2012
Did you look on LPCWare - this seems to be where NXP are putting a lot of examples these days.
http://www.lpcware.com

[lpcware]

Content originally posted in LPCWare by MikeSimmonds on Fri Apr 20 02:33:37 MST 2012
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Quote: researchinnovation
Hi..
On Code Red IDE something has given on the following place, it may help you.

http://ics.nxp.com/support/lpcxpresso/[/SIZE][/FONT]  [FONT=Tahoma][SIZE=2]

Thanks & Regards...[/SIZE][/FONT][FONT=Tahoma] [/FONT][FONT=Tahoma][SIZE=2]:)

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Thanks, I have seen these. They don't have any eamples either. :([/SIZE][/FONT]

[lpcware]

Content originally posted in LPCWare by researchinnovation on Fri Apr 20 02:26:29 MST 2012
Hi..
On Code Red IDE something has given on the following place, it may help you.

http://ics.nxp.com/support/lpcxpresso/

Thanks & Regards...:)

[lpcware]

Content originally posted in LPCWare by Polux rsv on Fri Apr 20 01:52:58 MST 2012
My personal thought about NXP example code: You will spend more time  debuging, correcting and/or making them to work, than writing your own  from scratch.

I admit the user manuals are hard to decode at first read. They miss diagrams to help understand devices structures and principles. But once you  get the way of understanding them, they are not as bad as you think.

Sorry not to be very helpful for your problem

Angelo