Content originally posted in LPCWare by Rob65 on Mon Nov 21 04:20:48 MST 2011
Quote: sasha75
But why erratic system clock/PLL programming should cause to chip fault???
Simply any combination that results in an invalid (e.g. too high) or not running (e.g. PLL switched as clock source but not running/locked/powered) will result in a non-functional CPU. There are warnings with a lot of the examples dealing with clock switching and PLL configuration about this.
To fix this, you can just pull the ISP pin (P2.10 on the 17xx) low and then connect/download with the LPC-Link module directly from the LPCXpresso tools.
Please note that before starting your application you need to make P2.10 high again, otherwise the ISP bootloader will start running instead of your code.
Cheers,
[INDENT]Rob
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