LPC15 IPR Confusion

[lpcware]

Content originally posted in LPCWare by R2D2 on Sun Nov 30 12:59:32 MST 2014
UM10736 is describing 'Interrupt Priority Registers':

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Quote:
The IPR0 register controls the priority of four peripheral interrupts. Each interrupt can
have one of 8 priorities, where 0 is the highest priority.

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So 4 interrupts in one 32 bit IPRx register 

Peripheral View in LPCXpresso is showing 'NVIC_IPR0'

Now it is 8 bit, one interrupt  :quest:

And CMSIS?

No IPR  :((

core_cm3.h:

__IO uint8_t  IP[240]; 

[lpcware]

Content originally posted in LPCWare by starblue on Tue Dec 02 05:25:49 MST 2014
Oh, sorry, somehow I didn't get that you were only discussing the peripheral view.

[lpcware]

Content originally posted in LPCWare by R2D2 on Mon Dec 01 08:50:16 MST 2014

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Quote: starblue
I'd recommend to use CMSIS functions to talk to the NVIC, in this case NVIC_SetPriority( IRQn, priority ).

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:quest:

I'm using NVIC_SetPriority  ;-)

Which is writing to IP[] registers...

Unfortunately that's not changing Peripheral View register names / sizes...

[lpcware]

Content originally posted in LPCWare by starblue on Mon Dec 01 07:49:17 MST 2014
I'd recommend to use CMSIS functions to talk to the NVIC, in this case NVIC_SetPriority( IRQn, priority ).

Beware that the priorities are specified differently from the hardware registers. In the registers the priority is in the most significant bits of each byte, while the routine expects them in the least significant bits.

[lpcware]

Content originally posted in LPCWare by R2D2 on Sun Nov 30 15:15:07 MST 2014

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Quote: lpcxpresso-support
Interrupt priority registers on Cortex-M3 can be treated as byte wide registers, or combined and treated as 4 interrupts inside a single word register.

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Would be less confusing if byte / word registers wouldn't use the same name...

[lpcware]

Content originally posted in LPCWare by lpcxpresso-support on Sun Nov 30 14:46:33 MST 2014
Interrupt priority registers on Cortex-M3 can be treated as byte wide registers, or combined and treated as 4 interrupts inside a single word register. The LPCXpresso peripheral view displays them in byte form (which is also how CMSIS headers handle them).

Also be aware, the NVIC peripheral displays were revamped a few releases ago, and some fixes related to the display of byte wide registers, such as the interrupt priority ones were also made in v7.50:

http://www.lpcware.com/content/forum/problem-lpcxpresso-display-nvic-registers

Regards,
LPCXpresso Support