LPC1343 Registers

[lpcware]

Content originally posted in LPCWare by lmoreira on Fri Jun 18 01:35:00 MST 2010
Hi Guys,
This is not directly connected with LPCXpresso, but is driving me nuts and you probably looked at the same thing and can give me some help.
I started having a look at how we the GPIOn is defined and how we use it and when I looked at the manual for the LPC1343 the memory sizes do not make sense. Roughly quoting the manual, the AHB memory alocation is 2MB and is divided to allow for 128 peripherals, hence each peripheral would be allocated 16KB. But When you look at the memory map for GPIO0 it will start at 0x50000000  and ends at 0x50010000 which is 65KB.
Any help welcomed.
Thanks
           Luis

[lpcware]

Content originally posted in LPCWare by NXP_Europe on Tue Jun 22 23:19:04 MST 2010
Hi All,
Double checked it and it seems you are (partially) right ;).
The AHB peripheral memory does contains 128 slots of 0x4000 bytes. The GPIO peripherals uses 4 slots because of the bit manipulation feature.
The memory map in section 2 therefore is wrong, see the attachment for the correct map.
This will be updated in the next release of the LPC1100 and LPC1300 user manual.

Great call!! Thanks for pointing this out!

[lpcware]

Content originally posted in LPCWare by lmoreira on Fri Jun 18 14:35:22 MST 2010
Hi NXP Europe,
The more I look at this the more I agree with Igor, there is some kind of error with your diagram or the statements you make on the manuals.
The two memory spaces do not tie-up as far as I am concern, if they do please can you clearly show how.
Thanks
Best Regards
                    Luis

[lpcware]

Content originally posted in LPCWare by igorsk on Fri Jun 18 11:57:24 MST 2010

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Quote: NXP_Europe
Hi Luis,
The GPIOs has a so called direct access mode, which allows you in a single write operation change GPIO bits without affecting other pins.
Masking registers are mapped on the lower addresses of the GPIO memory range (0x000 - 0x3FF8). See table 113 in chapter 8.4 of the user manual.
Chapter 8.5 explains how this works.
Because of the wide masking, more memory space is used then you'd expect.

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The issue is that if you divide AHB space by 128, you get [B]0x4000[/B] (0x200000 / 128), while on the memory map diagram (in chapter 2) each GPIO port is shown to occupy a single peripheral "slot" of [B]0x10000[/B]. So you need to either fix the diagram to show each GPIO taking up 4 slots or divide the AHB space into 32 slots instead of 128.

[lpcware]

Content originally posted in LPCWare by NXP_Europe on Fri Jun 18 11:05:30 MST 2010
Hi Luis,
The GPIOs has a so called direct access mode, which allows you in a single write operation change GPIO bits without affecting other pins.
Masking registers are mapped on the lower addresses of the GPIO memory range (0x000 - 0x3FF8). See table 113 in chapter 8.4 of the user manual.
Chapter 8.5 explains how this works.

Because of the wide masking, more memory space is used then you'd expect.

Kind regards,