Content originally posted in LPCWare by spongehead on Tue Feb 26 02:15:56 MST 2013
I am running with an LPC1227 module. I have 32-bit Timer 0 (CT32B0) configured for PWM. Per the "PWM Rules" section of Users Manual,
it indicates that the generated pulse will be LOW for whatever the MR0 {in my case) is set for and HIGH to the end of the period (MR3 in my case).
Does anyone know a way to "invert" this pulse behavior, such that the MR0
output is "HIGH" till MR0 count and then will go "LOW" for remainder of the
period. Don't want to add inverters on MR0-2 outputs if it can be done by some internal register setting that I am unaware of.
Any info appreciated!
