LPC11Uxx set_pll error

[lpcware]

Content originally posted in LPCWare by steven_ece on Wed May 23 10:43:39 MST 2012
EDIT: 5/25/2012 I have tracked the problem down to this. I checked the stack frame to see the last PC and then reset the system and stepped to that instruction which is ldr r3, [r3, #0] and r3 = 0x78C04821. In the ARM CORTEX M0 Generic User Guide this address should be external ram, none that I am aware of! Also I am not able to view anything at this location in the IDE. I checked the pointer into the boot rom and that was correct, so why am I getting here? Has anybody else experienced this?

Hello again,

Teh following is the code I am using on the LPC11u14. I wanted to see how set_pll worked so I am calling it in clockOpen and end up in the fault handler. I stepped through the disassembly and the fault happens after several load instructions. Any ideas on what I am missing?

/*
 * powerProfiles.c
 *
 *  Created on: May 21, 2012
 *      Author: surrender
 */

#include "LPC11Uxx.h"


#define CLKOUT 1

// set_pll mode options
#define CPU_FREQ_EQU 0
#define CPU_FREQ_LTE 1
#define CPU_FREQ_GTE 2
#define CPU_FREQ_APPROX 3
// set_pll result0 options
#define PLL_CMD_SUCCESS 0
#define PLL_INVALID_FREQ 1
#define PLL_INVALID_MODE 2
#define PLL_FREQ_NOT_FOUND 3
#define PLL_NOT_LOCKED 4

typedef struct _PWRD{
void(*set_pll)(unsigned int cmd[], unsigned int resp[]);
void(*set_power)(unsigned int cmd[], unsigned int resp[]);
}PWRD;

typedef struct _ROM{
const PWRD *pPWRD;
}ROM;

ROM **rom = (ROM **)(0x1FFF1FF8 + (3 * sizeof(ROM**))); // <#! BUG FROM THE USER MANUAL - change to ROM **rom = (ROM **)0x1FFF1FF8 !#>
unsigned int command[4], result[2];

/*
 * ============================================================================
 * Function : - Sets the PLL source to system oscillator
 *            - Sets the main clock source to the PLL input source
 *            - Sets the system clock divider to 1
 * ============================================================================
 */
void ppInit( void ){
uint32_t i;
/* Power on main oscillator */
LPC_SYSCON->PDRUNCFG &= ~(0x01<<5); /* Power on the system oscillator */
for(i = 0; i < 30000; i++); /* Wait for clock to stabalize */

/* Set PLL clock source to system oscillator */
LPC_SYSCON->SYSPLLCLKSEL = 0x01; /* Set PLL clock source to system oscillator */
LPC_SYSCON->SYSPLLCLKUEN = 0x00; /* Update clock source */
while(LPC_SYSCON->SYSPLLCLKUEN); /* Wait for update */
LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update clock source */
while(!(LPC_SYSCON->SYSPLLCLKUEN)); /* Wait for update */

/* Set main clock source to PLL input */
LPC_SYSCON->MAINCLKSEL = 0x01; /* Set main clock source to PLL input */
LPC_SYSCON->MAINCLKUEN = 0x00; /* Update clock source */
while(LPC_SYSCON->MAINCLKUEN); /* Wait for update */
LPC_SYSCON->MAINCLKUEN = 0x01; /* Update clock source */
while(!(LPC_SYSCON->MAINCLKUEN)); /* Wait for update */

/* Set system clock divider defaults to 1 */

#if CLKOUT
    /* Output clock to io pin */
    LPC_IOCON->PIO0_1 = 0x01; /* Enable clock out function on pin0_1 */
    LPC_SYSCON->CLKOUTSEL = 0x03; /* Main clock frequency */
    LPC_SYSCON->CLKOUTDIV = 24; /* Divide by 24 */
    LPC_SYSCON->CLKOUTUEN = 0x00;
    while(LPC_SYSCON->CLKOUTUEN & 0x01); /* Wait for update */
    LPC_SYSCON->CLKOUTUEN = 0x01;
    while(!(LPC_SYSCON->CLKOUTUEN & 0x01)); /* Wait for update */
#endif /* CLKOUT */
}

void clockOpen( void ){
ppInit(); /* Initialize components for set_pll routine */
command[0] = 12000;
command[1] = 25000;
command[2] = CPU_FREQ_LTE;
command[3] = 0;
(*rom)->pPWRD->set_pll(command,result);
}

[lpcware]

Content originally posted in LPCWare by steven_ece on Sun May 27 15:07:42 MST 2012
I thought I would gives this one more look. I checked back here and still nothing from the support staff. It looks like LPC11Uxx User Manual rev. 2.1 and example code contains an error.

In the previous code at the top of this thread the line below should have concerned anyone who has got set_pll to work

ROM **rom = (ROM **)(0x1FFF1FF8 + (3 * sizeof(ROM**)));

Instead it should be

ROM **rom = (ROM **)0x1FFF1FF8;

This error is on page 53. I also saw it in some example code somewhere. I don't remember where it is.

When I get a chance I will post a link to the project I used to test this.

[lpcware]

Content originally posted in LPCWare by steven_ece on Sun May 27 09:13:38 MST 2012
I will probably just write my own power management profiles, but I would like to know if I missed something about the ROM based APIs. At this point I am still getting to know my way around with this MCU.

Are they supposed to be on an external RAM?

What did I miss in the setup in order for me to successfully use the APIs?