LPC111x clocks

[lpcware]

Content originally posted in LPCWare by rkiryanov on Thu Feb 11 05:05:11 MST 2010
UM (11 January 2010), Fig 3. LPC111x CGU block diagram points that SPI0_PCLK is sourced directly from "main clock". Top right corner of this figure points that "AHB clocks 1 to 18 (memories and peripherals)" (I don't understand, how it can affect if peripherals are connected before this block). In PLC2xxx all peripheral clocks is sourced after CCLK and clocking directly from "main clock" is something new. What is correct?

[lpcware]

Content originally posted in LPCWare by NXP_Europe on Tue Feb 23 01:03:44 MST 2010
Hi rkiryanov
It looks like there have slipped a typo in the example code, it will be fixed in the next version. Sorry for that.

The variable SystemCoreClock actually represents the AHB clock frequency not the actual system core clock frequency, see system_LPC11xx.c line 394. So to be able to calculate the right baudrate, the SystemCoreClock must be multiplied with the SYSAHBCLKDIV to have the main clock frequency again.

So it actually shoud be:

regVal = SYSCON->UARTCLKDIV;
Fdiv = (((SystemCoreClock[COLOR=Red][B]*[/B][/COLOR]LPC_SYSCON->SYSAHBCLKDIV)/regVal)/16)/baudrate ;    /*baud rate */

So the user manual is (as always) leading

I hope this helps!

Kind regards,

[lpcware]

Content originally posted in LPCWare by rkiryanov on Thu Feb 18 02:16:19 MST 2010
up

[lpcware]

Content originally posted in LPCWare by rkiryanov on Sun Feb 14 03:28:39 MST 2010

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Quote: Gerrit
So the answer is [B]main_clock / SSP0CLKDIV[/B]Cheers

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Hello, Gerrit!

Look again to figure 3. What about UART_PCLK? Figure 3 says that it is also [B]main_clock / UARTCLKDIV[/B] and lets look to

http://ics.nxp.com/support/lpcxpresso/zip/lpc1114.examples.zip/uart/src/uart.c

lines 171-173:

  regVal = LPC_SYSCON->UARTCLKDIV;

  Fdiv = (((SystemCoreClock/LPC_SYSCON->SYSAHBCLKDIV)/regVal)/16)/baudrate ;/*baud rate */

it says that UART_PCLK is [B]main_clock / SYSAHBCLKDIV / UARTCLKDIV[/B]

Cool, huh?

[lpcware]

Content originally posted in LPCWare by Gerrit on Sun Feb 14 03:19:01 MST 2010
Hi rkiryanov,
Chapter 3.3 states:
The SYSAHBCLKCTRL register gates the system clock to the various peripherals and memories. UART, the WDT, and SPI0/1 have individual clock dividers to derive peripheral clocks from the main clock.

It is also depicted in Fig 3.
So the answer is [B]main_clock / SSP0CLKDIV[/B]

Cheers

[lpcware]

Content originally posted in LPCWare by rkiryanov on Fri Feb 12 00:34:17 MST 2010
In other words, what is SPI0_PCLK?

1: main_clock / SSP0CLKDIV
or
2: main_clock / SYSAHBCLKDIV / SSP0CLKDIV